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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by CO1NAM11FT039.mail.protection.outlook.com (10.13.174.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5353.14 via Frontend Transport; Tue, 21 Jun 2022 08:11:21 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 21 Jun 2022 08:11:17 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 21 Jun 2022 01:11:15 -0700 From: Xueming Li To: Jeff Daly CC: Qi Zhang , dpdk stable Subject: patch 'net/ixgbe: add option for link up check on pin SDP3' has been queued to stable release 20.11.6 Date: Tue, 21 Jun 2022 11:02:40 +0300 Message-ID: <20220621080301.2315720-95-xuemingl@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220621080301.2315720-1-xuemingl@nvidia.com> References: <20220621080301.2315720-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c025a482-e8ef-4d06-6374-08da535da085 X-MS-TrafficTypeDiagnostic: BL1PR12MB5192:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(376002)(396003)(39860400002)(346002)(136003)(46966006)(40470700004)(36840700001)(81166007)(966005)(40460700003)(36860700001)(82310400005)(316002)(6916009)(478600001)(86362001)(83380400001)(7696005)(16526019)(54906003)(186003)(41300700001)(2616005)(6666004)(356005)(336012)(82740400003)(26005)(6286002)(4326008)(426003)(53546011)(47076005)(36756003)(40480700001)(8936002)(5660300002)(2906002)(8676002)(40140700001)(70586007)(70206006)(1076003)(55016003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2022 08:11:21.5413 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c025a482-e8ef-4d06-6374-08da535da085 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5192 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 20.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 06/23/22. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/43eac062d1116e8e50276cb46f8867eb4f78717e Thanks. Xueming Li --- >From 43eac062d1116e8e50276cb46f8867eb4f78717e Mon Sep 17 00:00:00 2001 From: Jeff Daly Date: Tue, 10 May 2022 14:57:25 -0400 Subject: [PATCH] net/ixgbe: add option for link up check on pin SDP3 Cc: Xueming Li [ upstream commit 0f9fb100f6c6ed1dcadaf76352f4b4f2bd5501f6 ] 1ca05831b9b added a check that SDP3 (used as a TX_DISABLE output to the SFP cage on these cards) is not asserted to avoid incorrectly reporting link up when the SFP's laser is turned off. ff8162cb957 limited this workaround to fiber ports This patch: * Adds devarg 'fiber_sdp3_no_tx_disable' not all fiber ixgbe devs use SDP3 as TX_DISABLE Fixes: 1ca05831b9b ("net/ixgbe: fix link status") Fixes: ff8162cb957 ("net/ixgbe: fix link status") Signed-off-by: Jeff Daly Acked-by: Qi Zhang --- doc/guides/nics/ixgbe.rst | 17 ++++++++++++++ drivers/net/ixgbe/ixgbe_ethdev.c | 39 +++++++++++++++++++++++++++++++- drivers/net/ixgbe/ixgbe_ethdev.h | 3 +++ 3 files changed, 58 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/ixgbe.rst b/doc/guides/nics/ixgbe.rst index 4f4d3b1c2c..388778a01d 100644 --- a/doc/guides/nics/ixgbe.rst +++ b/doc/guides/nics/ixgbe.rst @@ -81,6 +81,23 @@ To guarantee the constraint, capabilities in dev_conf.rxmode.offloads will be ch fdir_conf->mode will also be checked. +Disable SDP3 TX_DISABLE for Fiber Links +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following ``devargs`` option can be enabled at runtime. It must +be passed as part of EAL arguments. For example, + +.. code-block:: console + + dpdk-testpmd -a fiber_sdp3_no_tx_disable=1 -- -i + +- ``fiber_sdp3_no_tx_disable`` (default **0**) + + Not all IXGBE implementations with SFP cages use the SDP3 signal as + TX_DISABLE as a means to disable the laser on fiber SFP modules. + This option informs the driver that in this case, SDP3 is not to be + used as a check for link up by testing for laser on/off. + VF Runtime Options ^^^^^^^^^^^^^^^^^^ diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 08d6bb66a5..3bd4a838e5 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -128,6 +128,13 @@ #define IXGBE_EXVET_VET_EXT_SHIFT 16 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 +#define IXGBE_DEVARG_FIBER_SDP3_NOT_TX_DISABLE "fiber_sdp3_no_tx_disable" + +static const char * const ixgbe_valid_arguments[] = { + IXGBE_DEVARG_FIBER_SDP3_NOT_TX_DISABLE, + NULL +}; + #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk" static const char * const ixgbevf_valid_arguments[] = { @@ -355,6 +362,8 @@ static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, static int ixgbe_filter_restore(struct rte_eth_dev *dev); static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw); +static int devarg_handle_int(__rte_unused const char *key, const char *value, + void *extra_args); /* * Define VF Stats MACRO for Non "cleared on read" register @@ -1039,6 +1048,29 @@ ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) ixgbe_release_swfw_semaphore(hw, mask); } +static void +ixgbe_parse_devargs(struct ixgbe_adapter *adapter, + struct rte_devargs *devargs) +{ + struct rte_kvargs *kvlist; + uint16_t sdp3_no_tx_disable; + + if (devargs == NULL) + return; + + kvlist = rte_kvargs_parse(devargs->args, ixgbe_valid_arguments); + if (kvlist == NULL) + return; + + if (rte_kvargs_count(kvlist, IXGBE_DEVARG_FIBER_SDP3_NOT_TX_DISABLE) == 1 && + rte_kvargs_process(kvlist, IXGBE_DEVARG_FIBER_SDP3_NOT_TX_DISABLE, + devarg_handle_int, &sdp3_no_tx_disable) == 0 && + sdp3_no_tx_disable == 1) + adapter->sdp3_no_tx_disable = 1; + + rte_kvargs_free(kvlist); +} + /* * This function is based on code in ixgbe_attach() in base/ixgbe.c. * It returns 0 on success. @@ -1103,6 +1135,8 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) } rte_atomic32_clear(&ad->link_thread_running); + ixgbe_parse_devargs(eth_dev->data->dev_private, + pci_dev->device.devargs); rte_eth_copy_pci_info(eth_dev, pci_dev); eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; @@ -4278,7 +4312,8 @@ ixgbe_dev_link_update_share(struct rte_eth_dev *dev, return rte_eth_linkstatus_set(dev, &link); } - if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { + if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber && + !ad->sdp3_no_tx_disable) { esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); if ((esdp_reg & IXGBE_ESDP_SDP3)) link_up = 0; @@ -8498,6 +8533,8 @@ ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe, + IXGBE_DEVARG_FIBER_SDP3_NOT_TX_DISABLE "=<0|1>"); RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h index 8d32088493..319a98cebf 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.h +++ b/drivers/net/ixgbe/ixgbe_ethdev.h @@ -510,6 +510,9 @@ struct ixgbe_adapter { /* For RSS reta table update */ uint8_t rss_reta_updated; + /* Used for limiting SDP3 TX_DISABLE checks */ + uint8_t sdp3_no_tx_disable; + /* Used for VF link sync with PF's physical and logical (by checking * mailbox status) link status. */ -- 2.35.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2022-06-21 15:37:53.451576636 +0800 +++ 0094-net-ixgbe-add-option-for-link-up-check-on-pin-SDP3.patch 2022-06-21 15:37:49.197785153 +0800 @@ -1 +1 @@ -From 0f9fb100f6c6ed1dcadaf76352f4b4f2bd5501f6 Mon Sep 17 00:00:00 2001 +From 43eac062d1116e8e50276cb46f8867eb4f78717e Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 0f9fb100f6c6ed1dcadaf76352f4b4f2bd5501f6 ] @@ -18 +20,0 @@ -Cc: stable@dpdk.org @@ -29 +31 @@ -index 82fa453fa2..ad1a3da610 100644 +index 4f4d3b1c2c..388778a01d 100644 @@ -32 +34 @@ -@@ -101,6 +101,23 @@ To guarantee the constraint, capabilities in dev_conf.rxmode.offloads will be ch +@@ -81,6 +81,23 @@ To guarantee the constraint, capabilities in dev_conf.rxmode.offloads will be ch @@ -57 +59 @@ -index 2da3f67bbc..f31bbb7895 100644 +index 08d6bb66a5..3bd4a838e5 100644 @@ -74 +76 @@ -@@ -348,6 +355,8 @@ static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, +@@ -355,6 +362,8 @@ static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, @@ -83 +85 @@ -@@ -1032,6 +1041,29 @@ ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) +@@ -1039,6 +1048,29 @@ ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) @@ -113 +115 @@ -@@ -1095,6 +1127,8 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) +@@ -1103,6 +1135,8 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) @@ -122 +124 @@ -@@ -4261,7 +4295,8 @@ ixgbe_dev_link_update_share(struct rte_eth_dev *dev, +@@ -4278,7 +4312,8 @@ ixgbe_dev_link_update_share(struct rte_eth_dev *dev, @@ -132 +134 @@ -@@ -8250,6 +8285,8 @@ ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) +@@ -8498,6 +8533,8 @@ ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) @@ -142 +144 @@ -index 69e0e82a5b..cc6049a66a 100644 +index 8d32088493..319a98cebf 100644 @@ -145 +147 @@ -@@ -501,6 +501,9 @@ struct ixgbe_adapter { +@@ -510,6 +510,9 @@ struct ixgbe_adapter {