From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F32D2A0032 for ; Wed, 20 Jul 2022 07:28:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DA3C840697; Wed, 20 Jul 2022 07:28:04 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 885324003C for ; Wed, 20 Jul 2022 07:28:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1658294882; x=1689830882; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=HpRE3mmy/O/BHNOiigy465CnVsvcKLT4OGYPSim3ks8=; b=mognHAQtEuyedAPI1shlwHC6vtMTkru+pEWU5E3frTD8l6aFNNUsYTOm iuKjE8qGETzuvC+XD3zIbs86x20j5IwJ9d8rEJfBVFdFGlOue6AnRIfi/ mNLntwzuhzYsXNOaW2QkehMjKU8nArv5qcSVkayn5+Q+Gz2iLzZZAAEC6 LBbVfwHcdf7H7V4tXhLbNBol4G6U8Tdbozoa+bjFosRIU15vsfTjQVfaZ EG6GLnRnBAcoPQEr9VPxhavb2wBxXVeVNdiQsyJFnVJ1HHNNSnzWmnZwt pResds5mFB5Ki1baMo15eS/069WnO0DhRsUNAzWSJCqgbaUxiQ8kTWu8I Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10413"; a="286692514" X-IronPort-AV: E=Sophos;i="5.92,286,1650956400"; d="scan'208";a="286692514" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2022 22:27:48 -0700 X-IronPort-AV: E=Sophos;i="5.92,286,1650956400"; d="scan'208";a="625511993" Received: from unknown (HELO localhost.localdomain) ([10.239.252.104]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2022 22:27:47 -0700 From: Ke Zhang To: stable@dpdk.org Cc: Ke Zhang Subject: [PATCH 19.11] net/iavf: fix Rx queue interrupt setting Date: Wed, 20 Jul 2022 13:19:26 +0800 Message-Id: <20220720051926.272674-1-ke1x.zhang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit a08f9cb698c3d4687765860e328dca727f7a516b ] For Rx-Queue Interrupt Setting, when vf rx interrupt disable(INTENA=0), there are two ways to write back descriptor to host memory: 1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register: Completed descriptors are posted to host memory according to the internal descriptor cache policy (in other words when a full cache line is available for write-back). A internal descriptor size is 16 bytes or 32 bytes, a cache line size is 64 bytes or 128 bytes from datasheet : PCIe Global Config 2 - GLPCI_CNF2 (0x000BE004; RO) so the full cache line could contains 4 packets, it means Network card will send 4 packets to host when a full cache line is available. 2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register: Completed descriptors also trigger the ITR. Following ITR expiration, all leftover completed descriptors are posted to host memory. Network card will send packet to host even if only one descriptor is completed. Changing 1) to 2) to make sure VF send the packet to host even if there is only one rx packet is ready in hardware. Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt") Cc: stable@dpdk.org Signed-off-by: Ke Zhang --- drivers/net/iavf/iavf_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index 3cb02bd1f..00a47bf13 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -1209,7 +1209,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) IAVF_WRITE_REG(hw, IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START), - 0); + IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK); IAVF_WRITE_FLUSH(hw); return 0; -- 2.25.1