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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by BN8NAM11FT004.mail.protection.outlook.com (10.13.176.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5458.17 via Frontend Transport; Wed, 20 Jul 2022 08:23:30 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Wed, 20 Jul 2022 08:23:29 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Wed, 20 Jul 2022 01:23:28 -0700 From: Xueming Li To: Jiawen Wu CC: , dpdk stable Subject: patch 'net/txgbe: fix register polling' has been queued to stable release 20.11.6 Date: Wed, 20 Jul 2022 11:20:49 +0300 Message-ID: <20220720082132.3954126-20-xuemingl@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220720082132.3954126-1-xuemingl@nvidia.com> References: <20220621080301.2315720-1-xuemingl@nvidia.com> <20220720082132.3954126-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2a45845e-1dae-483f-1a3b-08da6a29211f X-MS-TrafficTypeDiagnostic: MN2PR12MB3311:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(376002)(346002)(136003)(396003)(40470700004)(36840700001)(46966006)(83380400001)(426003)(336012)(47076005)(356005)(54906003)(82740400003)(26005)(81166007)(2616005)(53546011)(6286002)(1076003)(186003)(5660300002)(7696005)(36860700001)(16526019)(55016003)(8936002)(2906002)(82310400005)(40460700003)(40480700001)(6666004)(8676002)(70206006)(36756003)(41300700001)(6916009)(70586007)(478600001)(316002)(4326008)(86362001)(966005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2022 08:23:30.6517 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a45845e-1dae-483f-1a3b-08da6a29211f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3311 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 20.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 07/22/22. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/9b4779bfacef303e0f417337601365b6ddb00059 Thanks. Xueming Li --- >From 9b4779bfacef303e0f417337601365b6ddb00059 Mon Sep 17 00:00:00 2001 From: Jiawen Wu Date: Wed, 22 Jun 2022 14:56:09 +0800 Subject: [PATCH] net/txgbe: fix register polling Cc: Xueming Li [ upstream commit aa08f3eb4ecf0997fd30ac073fcd895db71ef8e3 ] Fix to poll some specific registers, which expect bit value 0. 'w32w' is used in registers where the write command bit is set and waits for the bit clear to complete the write. Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers") Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 3314975935..2802e59e16 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1817,8 +1817,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, } do { - all |= rd32(hw, reg); - value |= mask & all; + if (expect != 0) { + all |= rd32(hw, reg); + value |= mask & all; + } else { + all = rd32(hw, reg); + value = mask & all; + } if (value == expect) break; @@ -1846,7 +1851,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, #define wr32w(hw, reg, val, mask, slice) do { \ wr32((hw), reg, val); \ - po32m((hw), reg, mask, mask, NULL, 5, slice); \ + po32m((hw), reg, mask, 0, NULL, 5, slice); \ } while (0) #define TXGBE_XPCS_IDAADDR 0x13000 -- 2.35.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2022-07-20 15:00:59.710167757 +0800 +++ 0020-net-txgbe-fix-register-polling.patch 2022-07-20 15:00:58.704333841 +0800 @@ -1 +1 @@ -From aa08f3eb4ecf0997fd30ac073fcd895db71ef8e3 Mon Sep 17 00:00:00 2001 +From 9b4779bfacef303e0f417337601365b6ddb00059 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit aa08f3eb4ecf0997fd30ac073fcd895db71ef8e3 ] @@ -12 +14,0 @@ -Cc: stable@dpdk.org @@ -20 +22 @@ -index 3139796911..911bb6e04e 100644 +index 3314975935..2802e59e16 100644 @@ -23 +25 @@ -@@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, +@@ -1817,8 +1817,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, @@ -39 +41 @@ -@@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, +@@ -1846,7 +1851,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,