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Mon, 15 Aug 2022 00:26:32 -0700 From: Dmitry Kozlyuk To: CC: Xueming Li , Luca Boccassi , Viacheslav Ovsiienko Subject: [PATCH] net/mlx5: fix MPRQ pool registration Date: Mon, 15 Aug 2022 10:26:30 +0300 Message-ID: <20220815072630.165931-1-dkozlyuk@nvidia.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d391fad4-49c6-4dd9-dcf1-08da7e8f7bdd X-MS-TrafficTypeDiagnostic: MWHPR1201MB2479:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8jDse8p8tHlAHW44su9nGIshO8/FzTtoH+tieBie+MT63sTgeCO1HzxfCOZZefAKlGttSBCKl2NGPYJm++jM4r3Q+uBZcydGUkavlW7hwz9g1fbX7vwGZ7rkB4SIwf0EN1XwbP/7itjLYAYasVqkK+zO1ZGroSyJAKw7Tfvc+Hp81zkQvDWAwInf58YdIEJXqJBQJGtehLuciU0wWKTUFnolM5Lq5IxC7R47hjMNWlRu6uD5d3gmqpwrRp3fyR1Uo0FwxaoMITC2sC+TVzYHKouJPaHhk4hQuni3B7Ms4RvpCS++EQYHFjY8zSb4OJCNBEGcunHswmvm890OhHU5s2t++wo+9oU1JO5XlsQemzlHxIHn6apXqJCbgPXJiW9gghJe0lCi0Z+zVVbgrhDrs+xaXRduRoEyy6WCevzZuSgP0ptfnWRBFT+hjwNciRppqToEwWl3xYQjcNKNwN03GGxl8NbeAzr1YvKgJCFuMi0GULOJNLeVZa8koI18QwmKWQ6QqTCwXvC+fZp6A8ZdEyTK+kfWozeFP4Ke/+lGRFIdI3NcHjbnV8IxH/V84bD2U3nB65PeeFPq7Ea4q6hsXYwCY9nrt5Yp4dx3Pvwmepj5zOb1n4vOEaNi4sY7LA6fRFsCXu0dulJ5xHI9iZ1dvd1Km0J1PAx7bRWLhUEjLe5aLH1e3mgfrbXfMT/JE/NtEaONzHMmuK3jagBWhtO3+yNdscb0ibKh1cTDuZa6NbJwBq1fqr7Zb02G2a6bx72MA0w4xvOIzYPuMjLRUKboGycn0syOPjsvcAtAYeoBFznPK3Lz8Gxe7MmD8b2+KJ+xh4zcE+/OURKWaLfjiTyiMQ== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(346002)(396003)(376002)(39860400002)(136003)(36840700001)(46966006)(40470700004)(70586007)(426003)(336012)(1076003)(107886003)(186003)(47076005)(6286002)(7696005)(2616005)(26005)(82310400005)(478600001)(41300700001)(40480700001)(55016003)(36756003)(86362001)(81166007)(83380400001)(356005)(40460700003)(82740400003)(36860700001)(316002)(8936002)(5660300002)(2906002)(6916009)(54906003)(70206006)(4326008)(8676002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2022 07:26:34.8813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d391fad4-49c6-4dd9-dcf1-08da7e8f7bdd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB2479 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org mlx5_mr_update_mp() was checking pktmbuf pool private flags. However, this function may be passed an MPRQ pool, which is not a pktmbuf pool and has no private data. Random data is accessed instead of pktmbuf flags, causing a crash. Move the flags check to the RxQ start and only for pools that are known to be of pktmbuf type. Fixes: 23b584d6cc85 ("net/mlx5: fix external buffer pool registration for Rx queue") Signed-off-by: Dmitry Kozlyuk Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_mr.c | 11 ----------- drivers/net/mlx5/mlx5_trigger.c | 21 +++++++++++++++++++-- 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c index 1dd14ddfe5..2a7fac8ad3 100644 --- a/drivers/net/mlx5/mlx5_mr.c +++ b/drivers/net/mlx5/mlx5_mr.c @@ -444,18 +444,7 @@ mlx5_mr_update_mp(struct rte_eth_dev *dev, struct mlx5_mr_ctrl *mr_ctrl, .mr_ctrl = mr_ctrl, .ret = 0, }; - uint32_t flags = rte_pktmbuf_priv_flags(mp); - if (flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF) { - /* - * The pinned external buffer should be registered for DMA - * operations by application. The mem_list of the pool contains - * the list of chunks with mbuf structures w/o built-in data - * buffers and DMA actually does not happen there, no need - * to create MR for these chunks. - */ - return 0; - } DRV_LOG(DEBUG, "Port %u Rx queue registering mp %s " "having %u chunks.", dev->data->port_id, mp->name, mp->nb_mem_chunks); diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index c8dc0398ea..9b82ee40fd 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -156,12 +156,29 @@ mlx5_rxq_start(struct rte_eth_dev *dev) mlx5_mr_update_mp(dev, &rxq_ctrl->rxq.mr_ctrl, rxq_ctrl->rxq.mprq_mp); } else { + struct rte_mempool *mp; + uint32_t flags; uint32_t s; - for (s = 0; s < rxq_ctrl->rxq.rxseg_n; s++) + /* + * The pinned external buffer should be + * registered for DMA operations by application. + * The mem_list of the pool contains + * the list of chunks with mbuf structures + * w/o built-in data buffers + * and DMA actually does not happen there, + * no need to create MR for these chunks. + */ + for (s = 0; s < rxq_ctrl->rxq.rxseg_n; s++) { + mp = rxq_ctrl->rxq.rxseg[s].mp; + flags = rte_pktmbuf_priv_flags(mp); + if (flags & + RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF) + continue; mlx5_mr_update_mp (dev, &rxq_ctrl->rxq.mr_ctrl, - rxq_ctrl->rxq.rxseg[s].mp); + mp); + } } ret = rxq_alloc_elts(rxq_ctrl); if (ret) -- 2.25.1