From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6C62BA034C for ; Fri, 19 Aug 2022 20:36:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5A53A427F7; Fri, 19 Aug 2022 20:36:18 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id 2A51F40694; Fri, 19 Aug 2022 20:36:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660934174; x=1692470174; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oo9vJhyInU5eFCZ7g/aNkP1a7z620wr7aXnTlolKCik=; b=YnocgneWQDfqiW1/pgfklkj0gmiWtAftfklEULglIh+7B85DTzCy42i3 dk356JtlzOknV6w/S4roy+OK4y+OtG2J/6Pu80sQD8tMLxyNttOhPF/hn uT75XCx93KJpIBgq7e9fsdO5Y5209bAvGAQNhmNV4l5BYIwki2UKd5qH0 WkrWFVAeJBg1s9soE3grb40WiVfE7kC+iEYNfKBMbKFJCOfkuS9U+L8vi TRr18uTvFFCPsd3MiUeJjHOs2IIe1vER6AB5q3BdQDvN0AH35wOmi3eHK mwqSqnLcKkJCgZooS7brc8Dm68ElvV2XAZwLVruC5hHGFHBOTALN6UqVa w==; X-IronPort-AV: E=McAfee;i="6500,9779,10444"; a="319107212" X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="319107212" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2022 11:36:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,248,1654585200"; d="scan'208";a="608296240" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga002.jf.intel.com with ESMTP; 19 Aug 2022 11:36:12 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v2 04/37] baseband/acc100: free SW ring mem for reconfiguration Date: Fri, 19 Aug 2022 19:31:24 -0700 Message-Id: <20220820023157.189047-5-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220820023157.189047-1-hernan.vargas@intel.com> References: <20220820023157.189047-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Free base address of unaligned memory for SW rings to manage the missed corner case when there is a reconfiguration. Fixes: 060e7672930 ("baseband/acc100: add queue configuration") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas --- drivers/baseband/acc100/rte_acc100_pmd.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 7349bb5bad..349b8be5c1 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -340,6 +340,8 @@ alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc100_device *d, int i = 0; uint32_t q_sw_ring_size = ACC100_MAX_QUEUE_DEPTH * get_desc_len(); uint32_t dev_sw_ring_size = q_sw_ring_size * num_queues; + /* Free first in case this is a reconfiguration */ + rte_free(d->sw_rings_base); /* Find an aligned block of memory to store sw rings */ while (i < ACC100_SW_RING_MEM_ALLOC_ATTEMPTS) { @@ -768,6 +770,7 @@ acc100_dev_close(struct rte_bbdev *dev) rte_free(d->tail_ptrs); rte_free(d->info_ring); rte_free(d->sw_rings_base); + rte_free(d->harq_layout); d->sw_rings_base = NULL; } /* Ensure all in flight HW transactions are completed */ @@ -4665,7 +4668,8 @@ poweron_cleanup(struct rte_bbdev *bbdev, struct acc100_device *d, } printf("Number of 5GUL engines %d\n", numEngines); - rte_free(d->sw_rings_base); + if (d->sw_rings_base != NULL) + rte_free(d->sw_rings_base); usleep(ACC100_LONG_WAIT); } -- 2.37.1