From: Shun Hao <shunh@nvidia.com>
To: <viacheslavo@nvidia.com>, <matan@nvidia.com>, <orika@nvidia.com>,
"Sean Zhang" <xiazhang@nvidia.com>
Cc: <dev@dpdk.org>, <rasland@nvidia.com>, <stable@dpdk.org>
Subject: [PATCH v1 1/3] net/mlx5: fix meter hierarchy with represented port item
Date: Sat, 17 Sep 2022 09:02:08 +0300 [thread overview]
Message-ID: <20220917060210.3332529-2-shunh@nvidia.com> (raw)
In-Reply-To: <20220917060210.3332529-1-shunh@nvidia.com>
There is a new item type represented_port, and currently it will fail
when using meter hierarchy in flow using represented_port match.
This patch fixes this fail by adding support for represented_port item
in meter hierarchy flow split.
Fixes: e8146c63 ("net/mlx5: support represented port item in flow rules")
Cc: stable@dpdk.org
Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/mlx5_flow.c | 10 +++++++---
drivers/net/mlx5/mlx5_flow.h | 3 +++
drivers/net/mlx5/mlx5_flow_dv.c | 20 ++++++++++++++++----
3 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 8c93a3f2e5..e93b6e144c 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -5337,7 +5337,7 @@ flow_meter_split_prep(struct rte_eth_dev *dev,
switch (item_type) {
case RTE_FLOW_ITEM_TYPE_PORT_ID:
- if (mlx5_flow_get_item_vport_id(dev, items, &flow_src_port, error))
+ case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT:
return -rte_errno;
if (!fm->def_policy && wks->policy->is_hierarchy &&
flow_src_port != priv->representor_id) {
@@ -11025,14 +11025,18 @@ int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev,
{
struct mlx5_priv *port_priv;
const struct rte_flow_item_port_id *pid_v;
+ uint32_t esw_mgr_port;
- if (item->type != RTE_FLOW_ITEM_TYPE_PORT_ID)
+ if (item->type != RTE_FLOW_ITEM_TYPE_PORT_ID &&
+ item->type != RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT)
return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
NULL, "Incorrect item type.");
pid_v = item->spec;
if (!pid_v)
return 0;
- if (pid_v->id == MLX5_PORT_ESW_MGR) {
+ esw_mgr_port = (item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) ?
+ MLX5_REPRESENTED_PORT_ESW_MGR : MLX5_PORT_ESW_MGR;
+ if (pid_v->id == esw_mgr_port) {
*vport_id = mlx5_flow_get_esw_manager_vport_id(dev);
} else {
port_priv = mlx5_port_to_eswitch_info(pid_v->id, false);
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 4c233cd94a..2f265763a9 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -21,6 +21,9 @@
/* E-Switch Manager port, used for rte_flow_item_port_id. */
#define MLX5_PORT_ESW_MGR UINT32_MAX
+/* E-Switch Manager port, used for rte_flow_item_ethdev. */
+#define MLX5_REPRESENTED_PORT_ESW_MGR UINT16_MAX
+
/* Private rte flow items. */
enum mlx5_rte_flow_item_type {
MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 4c811fe00a..f7a5e479b6 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7055,6 +7055,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
if (ret < 0)
return ret;
last_item = MLX5_FLOW_ITEM_REPRESENTED_PORT;
+ port_id_item = items;
break;
case RTE_FLOW_ITEM_TYPE_ETH:
ret = mlx5_flow_validate_item_eth(items, item_flags,
@@ -16642,8 +16643,13 @@ __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
uint8_t misc_mask;
if (match_src_port && priv->sh->esw_mode) {
- if (flow_dv_translate_item_port_id(dev, matcher.buf,
- value.buf, item, attr)) {
+ if (item && item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT)
+ ret = flow_dv_translate_item_represented_port(dev, matcher.buf, value.buf,
+ item, attr);
+ else
+ ret = flow_dv_translate_item_port_id(dev, matcher.buf, value.buf,
+ item, attr);
+ if (ret) {
DRV_LOG(ERR, "Failed to create meter policy%d flow's"
" value with port.", color);
return -1;
@@ -16692,10 +16698,16 @@ __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
struct mlx5_flow_tbl_data_entry *tbl_data;
struct mlx5_priv *priv = dev->data->dev_private;
const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
+ int ret;
if (match_src_port && priv->sh->esw_mode) {
- if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
- value.buf, item, attr)) {
+ if (item && item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT)
+ ret = flow_dv_translate_item_represented_port(dev, matcher.mask.buf,
+ value.buf, item, attr);
+ else
+ ret = flow_dv_translate_item_port_id(dev, matcher.mask.buf, value.buf,
+ item, attr);
+ if (ret) {
DRV_LOG(ERR, "Failed to register meter policy%d matcher"
" with port.", priority);
return -1;
--
2.20.0
next parent reply other threads:[~2022-09-17 6:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220917060210.3332529-1-shunh@nvidia.com>
2022-09-17 6:02 ` Shun Hao [this message]
2022-09-17 6:02 ` [PATCH v1 2/3] net/mlx5: add meter flow limitation when matching all ports Shun Hao
2022-09-17 6:02 ` [PATCH v1 3/3] net/mlx5: fix meter ID tag for meter hierarchy Shun Hao
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