From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3E863A0552 for ; Thu, 20 Oct 2022 23:24:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AC9D342B79; Thu, 20 Oct 2022 23:24:38 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 28D8A410D1; Thu, 20 Oct 2022 23:24:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666301076; x=1697837076; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4DPT98XI4fS3hau6ILjk8vdTvRJtbvlyCfXywxkkVVs=; b=ZfYC/5I0vVwjU+764GO1gbvNsshwWxBTMGBfEF8EqaJRsEKB025pq7Sx o/QGPWTvYQU1TB7x4l/v1CGll4q2DV/4na3djZqZBW70NeyFPELQhOfMA CCjoB2GHT9OMENMEtAIEy/lb0y6v6ufH6ojfkM7i+z7icqgriqNnaKfTU Ob0oXPMTik9FoirCkJADEmT0wzTppoDiTnGkDZlyhkfTcek4+Q4sGukzW kPH9ynNVn0i7pfFCssmtabDXVIVUwX19lZw1+d1ZVF7N2gMwVDICO2zB+ VeC0JIp1BypjDU0/YA+IrR76Bysy8/YD3S5hEgz2Y+/dIdMUml3jfP+dQ Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="368887452" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="368887452" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 14:24:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="755396799" X-IronPort-AV: E=Sophos;i="5.95,199,1661842800"; d="scan'208";a="755396799" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga004.jf.intel.com with ESMTP; 20 Oct 2022 14:24:29 -0700 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v5 02/29] baseband/acc100: add function to check AQ availability Date: Thu, 20 Oct 2022 22:20:35 -0700 Message-Id: <20221021052102.107141-3-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221021052102.107141-1-hernan.vargas@intel.com> References: <20221021052102.107141-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org It is possible for some corner case to run more batch enqueue than supported. A protection is required to avoid that corner case. Enhance all ACC100 enqueue operations with check to see if there is room in the atomic queue for enqueueing batches into the queue manager Check room in AQ for the enqueues batches into Qmgr Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas --- drivers/baseband/acc/rte_acc100_pmd.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c index 3b0c8e41dc..7fec2283eb 100644 --- a/drivers/baseband/acc/rte_acc100_pmd.c +++ b/drivers/baseband/acc/rte_acc100_pmd.c @@ -2983,7 +2983,8 @@ static uint16_t acc100_enqueue_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc_aq_avail(q_data, num); + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_enc_tb(q_data, ops, num); @@ -2996,7 +2997,8 @@ static uint16_t acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc_aq_avail(q_data, num); + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_enc_tb(q_data, ops, num); @@ -3164,8 +3166,11 @@ static uint16_t acc100_enqueue_dec(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc_aq_avail(q_data, num); + + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; + if (ops[0]->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_dec_tb(q_data, ops, num); else @@ -3177,11 +3182,9 @@ static uint16_t acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { - struct acc_queue *q = q_data->queue_private; - int32_t aq_avail = q->aq_depth + - (q->aq_dequeued - q->aq_enqueued) / 128; + int32_t aq_avail = acc_aq_avail(q_data, num); - if (unlikely((aq_avail == 0) || (num == 0))) + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) @@ -3190,7 +3193,6 @@ acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, return acc100_enqueue_ldpc_dec_cb(q_data, ops, num); } - /* Dequeue one encode operations from ACC100 device in CB mode */ static inline int dequeue_enc_one_op_cb(struct acc_queue *q, struct rte_bbdev_enc_op **ref_op, -- 2.37.1