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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CO1NAM11FT021.mail.protection.outlook.com (10.13.175.51) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.12 via Frontend Transport; Wed, 9 Nov 2022 16:51:07 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Wed, 9 Nov 2022 08:50:54 -0800 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 9 Nov 2022 08:50:52 -0800 From: Gregory Etelson To: CC: , , , , Viacheslav Ovsiienko Subject: [PATCH] net/mlx5: fix port initialization with small LRO Date: Wed, 9 Nov 2022 18:50:38 +0200 Message-ID: <20221109165038.1049-1-getelson@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT021:EE_|PH7PR12MB7353:EE_ X-MS-Office365-Filtering-Correlation-Id: 1563eff5-c205-4bcb-35aa-08dac27298f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2022 16:51:07.3519 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1563eff5-c205-4bcb-35aa-08dac27298f5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7353 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org If application provided maximal LRO size was less than expected PMD minimum, the PMD either crashed with assert, if asserts were enabled, or proceeded with port initialization to set port private maximal LRO size below supported minimum. The patch terminates port start if LRO size does not match PMD requirements and TCP LRO offload was requested at least for one Rx queue. Fixes: 50c00baff763 ("net/mlx5: limit LRO size to maximum Rx packet") Cc: stable@dpdk.org Signed-off-by: Gregory Etelson Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_rxq.c | 1 - drivers/net/mlx5/mlx5_trigger.c | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 0d9d11680b..724cd6c7e6 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -1533,7 +1533,6 @@ mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx, MLX5_MAX_TCP_HDR_OFFSET) max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET; max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE); - MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE); max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE; if (priv->max_lro_msg_size) priv->max_lro_msg_size = diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 4b821a1076..71089299b8 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1167,6 +1167,22 @@ mlx5_dev_start(struct rte_eth_dev *dev) else rte_net_mlx5_dynf_inline_mask = 0; if (dev->data->nb_rx_queues > 0) { + uint32_t max_lro_msg_size = priv->max_lro_msg_size; + + if (max_lro_msg_size < MLX5_LRO_SEG_CHUNK_SIZE) { + uint32_t i; + struct mlx5_rxq_priv *rxq; + + for (i = 0; i != priv->rxqs_n; ++i) { + rxq = mlx5_rxq_get(dev, i); + if (rxq && rxq->ctrl && rxq->ctrl->rxq.lro) { + DRV_LOG(ERR, "port %u invalid max LRO size", + dev->data->port_id); + rte_errno = EINVAL; + return -rte_errno; + } + } + } ret = mlx5_dev_configure_rss_reta(dev); if (ret) { DRV_LOG(ERR, "port %u reta config failed: %s", -- 2.34.1