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From: Michael Baum <michaelba@nvidia.com>
To: <dev@dpdk.org>
CC: Matan Azrad <matan@nvidia.com>, Akhil Goyal <gakhil@marvell.com>, "Thomas
Monjalon" <thomas@monjalon.net>, <stable@dpdk.org>
Subject: [PATCH 1/7] compress/mlx5: fix wrong output Adler-32 checksum offset
Date: Mon, 9 Jan 2023 09:58:32 +0200
Message-ID: <20230109075838.2508039-2-michaelba@nvidia.com>
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Errors-To: stable-bounces@dpdk.org
After de/compress dequeue, the output checksum is copied into the op
structure. The "output_checksum" field in op structure is "uint64_t"
type, and the 32-bit checksums (CRC32, Adler-32) are copied into the
lower 32 bits.
When both CRC32 and Adler-32 are configured, CRC32 is copied into the
lower 32 bits and Adler-32 into the upper 32 bits.
However, in mlx5 PMD Adler-32 without CRC, is mistakenly copied into the
upper 32 bits.
This patch updates Adler-32 output checksun to be copied into the
lower 32 bits.
Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions")
Cc: matan@nvidia.com
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
drivers/compress/mlx5/mlx5_compress.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 459e4b5e8a..c0a861e5e4 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -633,7 +633,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
break;
case RTE_COMP_CHECKSUM_ADLER32:
op->output_chksum = (uint64_t)rte_be_to_cpu_32
- (opaq[idx].adler32) << 32;
+ (opaq[idx].adler32);
break;
case RTE_COMP_CHECKSUM_CRC32_ADLER32:
op->output_chksum = (uint64_t)rte_be_to_cpu_32
--
2.25.1