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Sun, 8 Jan 2023 23:58:47 -0800 From: Michael Baum To: CC: Matan Azrad , Akhil Goyal , "Thomas Monjalon" , Subject: [PATCH 1/7] compress/mlx5: fix wrong output Adler-32 checksum offset Date: Mon, 9 Jan 2023 09:58:32 +0200 Message-ID: <20230109075838.2508039-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230109075838.2508039-1-michaelba@nvidia.com> References: <20230109075838.2508039-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT056:EE_|BY5PR12MB4212:EE_ X-MS-Office365-Filtering-Correlation-Id: ccecf1c8-45a6-4c75-9fd9-08daf2175e26 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: baFUZVWj3+5fl7EtAWuPji0wfGNc/Z3LgrYv/DXceFZKosObq5wSZbMOGUL9VajPfAfHbG1bmV74bHyjFrgpvDleMYLQ4Y6Dd9bn7kYk0CkjqYsx1kV470zCP/6FsXSEOEtGnReRZMJdIg+Ypvd2WFmHlObCq8WRdlaOKsx/NoyIKzkf58WKtJxJ+DMKPOgNebbSHM6ntDa5uHzSpuIaY9kbMGCGpMs+g3AhdNq2Yfvv8K2ieoUUNr6xWOJsilaBKxqa5HtYo1NjKEK5REa54+ux5erQWzLHiwefB7tMV1t8olayS1DbiQlTPyZeDp/HtpnA2MMvTOZ82/OIpm9ntMrHzm4vyVzyV8uWqHlbqBhE2UXS5gDH8ZO0IO4U9dCH0xcB4kh4nmhSAniuCgyZ6srOz6/Olm+Y5Wj8iwFpmIDuBEjZsxi9w39LEPJO6d7bN8n9V7mmI4wTKSijwm/F0Uo44ch4uX63Af3or0t2t6V7DfMommtwFrChVVrhvu5Nh9qnpXrfY9Z239UYisXo4GX1lWfKAISgPWXaEbchRS0ZZA7wZlkecsE9pZfnGLZ6/Ry82ly+/a6pZOCv90/vVxQ8tZozDFJdjNdHnETidx0SFWYZlyHWk82kXHFp057YDbYsIGlH+Pl4S00i5/NWntnVzyV6lOdDJ8LZRTCPTWw= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(136003)(39850400004)(376002)(346002)(451199015)(36840700001)(46966006)(36756003)(186003)(8936002)(6666004)(26005)(2616005)(1076003)(54906003)(5660300002)(55016003)(40480700001)(7696005)(6286002)(6916009)(4326008)(316002)(356005)(86362001)(82740400003)(70586007)(478600001)(7636003)(41300700001)(70206006)(8676002)(82310400005)(47076005)(2906002)(83380400001)(426003)(336012)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jan 2023 07:59:00.2543 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ccecf1c8-45a6-4c75-9fd9-08daf2175e26 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4212 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org After de/compress dequeue, the output checksum is copied into the op structure. The "output_checksum" field in op structure is "uint64_t" type, and the 32-bit checksums (CRC32, Adler-32) are copied into the lower 32 bits. When both CRC32 and Adler-32 are configured, CRC32 is copied into the lower 32 bits and Adler-32 into the upper 32 bits. However, in mlx5 PMD Adler-32 without CRC, is mistakenly copied into the upper 32 bits. This patch updates Adler-32 output checksun to be copied into the lower 32 bits. Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions") Cc: matan@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum --- drivers/compress/mlx5/mlx5_compress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 459e4b5e8a..c0a861e5e4 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -633,7 +633,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops, break; case RTE_COMP_CHECKSUM_ADLER32: op->output_chksum = (uint64_t)rte_be_to_cpu_32 - (opaq[idx].adler32) << 32; + (opaq[idx].adler32); break; case RTE_COMP_CHECKSUM_CRC32_ADLER32: op->output_chksum = (uint64_t)rte_be_to_cpu_32 -- 2.25.1