* [PATCH] net/mlx5: check compressed CQE opcode for an error
@ 2023-01-27 3:23 Alexander Kozyrev
2023-02-06 15:05 ` Matan Azrad
2023-02-12 13:37 ` Raslan Darawsheh
0 siblings, 2 replies; 3+ messages in thread
From: Alexander Kozyrev @ 2023-01-27 3:23 UTC (permalink / raw)
To: dev; +Cc: stable, rasland, matan, viacheslavo
The CQE opcode is never checked for a compressed CQE in
the vectorized Rx burst routines. It is assumed that
compressed CQEs are always valid and skipped error checking.
This is obviously not the case and error CQEs may be
compressed together as well. Need to check for the
MLX5_CQE_RESP_ERR opcode and mark all the packets as
bad ones in the compression session if it is there.
Note that this issue is not applicable to the scalar Rx burst.
Fixes: 6cb559d67b ("net/mlx5: add vectorized Rx/Tx burst for x86")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 16 +++++++++++++---
drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 10 +++++++---
drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 9 ++++++---
3 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
index 683a8f9a6c..204d17a8f2 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h
@@ -783,7 +783,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
{
const uint16_t q_n = 1 << rxq->cqe_n;
const uint16_t q_mask = q_n - 1;
- unsigned int pos;
+ unsigned int pos, adj;
uint64_t n = 0;
uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
uint16_t nocmp_n = 0;
@@ -866,7 +866,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
__vector unsigned char pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
__vector unsigned char op_own, op_own_tmp1, op_own_tmp2;
__vector unsigned char opcode, owner_mask, invalid_mask;
- __vector unsigned char comp_mask;
+ __vector unsigned char comp_mask, mini_mask;
__vector unsigned char mask;
#ifdef MLX5_PMD_SOFT_COUNTERS
const __vector unsigned char lower_half = {
@@ -1174,6 +1174,16 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
(__vector unsigned long)mask);
/* D.3 check error in opcode. */
+ adj = (comp_idx != MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n);
+ mask = (__vector unsigned char)(__vector unsigned long){
+ (adj * sizeof(uint16_t) * 8), 0};
+ lshift = vec_splat((__vector unsigned long)mask, 0);
+ shmask = vec_cmpgt(shmax, lshift);
+ mini_mask = (__vector unsigned char)
+ vec_sl((__vector unsigned long)invalid_mask, lshift);
+ mini_mask = (__vector unsigned char)
+ vec_sel((__vector unsigned long)shmask,
+ (__vector unsigned long)mini_mask, shmask);
opcode = (__vector unsigned char)
vec_cmpeq((__vector unsigned int)resp_err_check,
(__vector unsigned int)opcode);
@@ -1182,7 +1192,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
(__vector unsigned int)zero);
opcode = (__vector unsigned char)
vec_andc((__vector unsigned long)opcode,
- (__vector unsigned long)invalid_mask);
+ (__vector unsigned long)mini_mask);
/* D.4 mark if any error is set */
*err |= ((__vector unsigned long)opcode)[0];
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
index f7bbde4e0e..41b9cf5444 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
@@ -524,7 +524,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
{
const uint16_t q_n = 1 << rxq->cqe_n;
const uint16_t q_mask = q_n - 1;
- unsigned int pos;
+ unsigned int pos, adj;
uint64_t n = 0;
uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
uint16_t nocmp_n = 0;
@@ -616,7 +616,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
pos += MLX5_VPMD_DESCS_PER_LOOP) {
uint16x4_t op_own;
uint16x4_t opcode, owner_mask, invalid_mask;
- uint16x4_t comp_mask;
+ uint16x4_t comp_mask, mini_mask;
uint16x4_t mask;
uint16x4_t byte_cnt;
uint32x4_t ptype_info, flow_tag;
@@ -780,8 +780,12 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
-1UL >> (n * sizeof(uint16_t) * 8) : 0);
invalid_mask = vorr_u16(invalid_mask, mask);
/* D.3 check error in opcode. */
+ adj = (comp_idx != MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n);
+ mask = vcreate_u16(adj ?
+ -1UL >> ((n + 1) * sizeof(uint16_t) * 8) : -1UL);
+ mini_mask = vand_u16(invalid_mask, mask);
opcode = vceq_u16(resp_err_check, opcode);
- opcode = vbic_u16(opcode, invalid_mask);
+ opcode = vbic_u16(opcode, mini_mask);
/* D.4 mark if any error is set */
*err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0);
/* C.4 fill in mbuf - rearm_data and packet_type. */
diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
index 185d2695db..ab69af0c55 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h
@@ -523,7 +523,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
{
const uint16_t q_n = 1 << rxq->cqe_n;
const uint16_t q_mask = q_n - 1;
- unsigned int pos;
+ unsigned int pos, adj;
uint64_t n = 0;
uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP;
uint16_t nocmp_n = 0;
@@ -591,7 +591,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
__m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
__m128i op_own, op_own_tmp1, op_own_tmp2;
__m128i opcode, owner_mask, invalid_mask;
- __m128i comp_mask;
+ __m128i comp_mask, mini_mask;
__m128i mask;
#ifdef MLX5_PMD_SOFT_COUNTERS
__m128i byte_cnt;
@@ -729,9 +729,12 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
mask = _mm_sll_epi64(ones, mask);
invalid_mask = _mm_or_si128(invalid_mask, mask);
/* D.3 check error in opcode. */
+ adj = (comp_idx != MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n);
+ mask = _mm_set_epi64x(0, adj * sizeof(uint16_t) * 8);
+ mini_mask = _mm_sll_epi64(invalid_mask, mask);
opcode = _mm_cmpeq_epi32(resp_err_check, opcode);
opcode = _mm_packs_epi32(opcode, zero);
- opcode = _mm_andnot_si128(invalid_mask, opcode);
+ opcode = _mm_andnot_si128(mini_mask, opcode);
/* D.4 mark if any error is set */
*err |= _mm_cvtsi128_si64(opcode);
/* D.5 fill in mbuf - rearm_data and packet_type. */
--
2.18.2
^ permalink raw reply [flat|nested] 3+ messages in thread* RE: [PATCH] net/mlx5: check compressed CQE opcode for an error
2023-01-27 3:23 [PATCH] net/mlx5: check compressed CQE opcode for an error Alexander Kozyrev
@ 2023-02-06 15:05 ` Matan Azrad
2023-02-12 13:37 ` Raslan Darawsheh
1 sibling, 0 replies; 3+ messages in thread
From: Matan Azrad @ 2023-02-06 15:05 UTC (permalink / raw)
To: Alexander Kozyrev, dev; +Cc: stable, Raslan Darawsheh, Slava Ovsiienko
From: Alexander Kozyrev
> The CQE opcode is never checked for a compressed CQE in the vectorized Rx
> burst routines. It is assumed that compressed CQEs are always valid and
> skipped error checking.
>
> This is obviously not the case and error CQEs may be compressed together as
> well. Need to check for the MLX5_CQE_RESP_ERR opcode and mark all the
> packets as bad ones in the compression session if it is there.
>
> Note that this issue is not applicable to the scalar Rx burst.
>
> Fixes: 6cb559d67b ("net/mlx5: add vectorized Rx/Tx burst for x86")
> Cc: stable@dpdk.org
>
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
^ permalink raw reply [flat|nested] 3+ messages in thread* RE: [PATCH] net/mlx5: check compressed CQE opcode for an error
2023-01-27 3:23 [PATCH] net/mlx5: check compressed CQE opcode for an error Alexander Kozyrev
2023-02-06 15:05 ` Matan Azrad
@ 2023-02-12 13:37 ` Raslan Darawsheh
1 sibling, 0 replies; 3+ messages in thread
From: Raslan Darawsheh @ 2023-02-12 13:37 UTC (permalink / raw)
To: Alexander Kozyrev, dev; +Cc: stable, Matan Azrad, Slava Ovsiienko
Hi,
> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Friday, January 27, 2023 5:23 AM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Matan
> Azrad <matan@nvidia.com>; Slava Ovsiienko <viacheslavo@nvidia.com>
> Subject: [PATCH] net/mlx5: check compressed CQE opcode for an error
>
> The CQE opcode is never checked for a compressed CQE in the vectorized Rx
> burst routines. It is assumed that compressed CQEs are always valid and
> skipped error checking.
>
> This is obviously not the case and error CQEs may be compressed together as
> well. Need to check for the MLX5_CQE_RESP_ERR opcode and mark all the
> packets as bad ones in the compression session if it is there.
>
> Note that this issue is not applicable to the scalar Rx burst.
>
> Fixes: 6cb559d67b ("net/mlx5: add vectorized Rx/Tx burst for x86")
> Cc: stable@dpdk.org
>
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Patch applied to next-net-mlx
Kindest regards,
Raslan Darawsheh
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-01-27 3:23 [PATCH] net/mlx5: check compressed CQE opcode for an error Alexander Kozyrev
2023-02-06 15:05 ` Matan Azrad
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