From: Jiawen Wu <jiawenwu@trustnetic.com>
To: dev@dpdk.org
Cc: Jiawen Wu <jiawenwu@trustnetic.com>, stable@dpdk.org
Subject: [PATCH v2 03/10] net/txgbe: fix default signal quality value for KX/KX4
Date: Thu, 2 Feb 2023 17:21:25 +0800 [thread overview]
Message-ID: <20230202092132.3271910-4-jiawenwu@trustnetic.com> (raw)
In-Reply-To: <20230202092132.3271910-1-jiawenwu@trustnetic.com>
On old firmware versions, the default value of signal quality(TX_EQ) is
configured by the driver. Fix it for KX/KX4 mode.
Fixes: 01c3cf5c85a7 ("net/txgbe: add autoneg control read and write")
Cc: stable@dpdk.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_phy.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index 9f46d5bdb0..87935abdaa 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -1693,9 +1693,10 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
} else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
value = (0x1804 & ~0x3F3F);
+ value |= 40 << 8;
wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
- value = (0x50 & ~0x7F) | 40 | (1 << 6);
+ value = (0x50 & ~0x7F) | (1 << 6);
wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
}
out:
@@ -1907,10 +1908,10 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,
value |= hw->phy.ffe_post | (1 << 6);
wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
} else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
- value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
+ value = (0x1804 & ~0x3F3F) | (40 << 8);
wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
- value = (0x50 & ~0x7F) | 16 | (1 << 6);
+ value = (0x50 & ~0x7F) | (1 << 6);
wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
}
out:
--
2.27.0
next prev parent reply other threads:[~2023-02-02 9:25 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230118060039.3074016-1-jiawenwu@trustnetic.com>
2023-01-18 6:00 ` [PATCH 1/8] net/txgbe: fix Rx buffer size in configure register Jiawen Wu
2023-01-27 15:36 ` Ferruh Yigit
2023-02-01 2:34 ` Jiawen Wu
2023-02-01 10:40 ` Ferruh Yigit
2023-01-18 6:00 ` [PATCH 2/8] net/txgbe: fix default signal quality value for KX/KX4 Jiawen Wu
2023-01-18 6:00 ` [PATCH 3/8] net/txgbe: fix packet type to parse from offload flags Jiawen Wu
2023-01-27 15:36 ` Ferruh Yigit
2023-02-01 3:14 ` Jiawen Wu
2023-02-01 10:41 ` Ferruh Yigit
2023-01-18 6:00 ` [PATCH 4/8] net/ngbe: " Jiawen Wu
2023-01-27 15:37 ` Ferruh Yigit
2023-01-18 6:00 ` [PATCH 5/8] net/ngbe: add spinlock protection on YT PHY Jiawen Wu
[not found] ` <20230202092132.3271910-1-jiawenwu@trustnetic.com>
2023-02-02 9:21 ` [PATCH v2 01/10] net/ngbe: fix Rx buffer size in configure register Jiawen Wu
2023-02-08 10:28 ` Ferruh Yigit
2023-02-09 9:00 ` Jiawen Wu
2023-02-14 8:15 ` Jiawen Wu
2023-02-14 9:55 ` Ferruh Yigit
2023-02-15 9:35 ` Ferruh Yigit
2023-02-15 10:09 ` Jiawen Wu
2023-02-02 9:21 ` [PATCH v2 02/10] net/txgbe: " Jiawen Wu
2023-02-02 9:21 ` Jiawen Wu [this message]
2023-02-02 9:21 ` [PATCH v2 04/10] net/txgbe: fix packet type to parse from offload flags Jiawen Wu
2023-02-02 9:21 ` [PATCH v2 05/10] net/ngbe: " Jiawen Wu
2023-02-02 9:21 ` [PATCH v2 06/10] net/ngbe: add spinlock protection on YT PHY Jiawen Wu
2023-02-02 9:21 ` [PATCH v2 09/10] net/txgbe: fix interrupt loss Jiawen Wu
2023-02-15 2:00 ` [PATCH v3] net/txgbe: fix Rx buffer size in configure register Jiawen Wu
2023-02-15 10:24 ` Ferruh Yigit
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