[PATCH 1/7] compress/mlx5: fix wrong output Adler-32 checksum offset

[PATCH 1/7] compress/mlx5: fix wrong output Adler-32 checksum offset

[Michael Baum]

After de/compress dequeue, the output checksum is copied into the op
structure. The "output_checksum" field in op structure is "uint64_t"
type, and the 32-bit checksums (CRC32, Adler-32) are copied into the
lower 32 bits.

When both CRC32 and Adler-32 are configured, CRC32 is copied into the
lower 32 bits and Adler-32 into the upper 32 bits.
However, in mlx5 PMD Adler-32 without CRC, is mistakenly copied into the
upper 32 bits.

This patch updates Adler-32 output checksun to be copied into the
lower 32 bits.

Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions")
Cc: matan@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
 drivers/compress/mlx5/mlx5_compress.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 459e4b5e8a..c0a861e5e4 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -633,7 +633,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 				break;
 			case RTE_COMP_CHECKSUM_ADLER32:
 				op->output_chksum = (uint64_t)rte_be_to_cpu_32
-					    (opaq[idx].adler32) << 32;
+						    (opaq[idx].adler32);
 				break;
 			case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 				op->output_chksum = (uint64_t)rte_be_to_cpu_32
-- 
2.25.1

[PATCH 2/7] compress/mlx5: fix QP setup for partial transformations

[Michael Baum]

The mlx5_compress_qp_setup() function creates QP for compress,
decompress and DMA. Thus, the MMO flag is turned on only when all
operations are supported.

However, since partial transformations have been allowed, it should be
turn on for part of them.

This patch removes the compress MMO support requirement.

Fixes: 2efd26544554 ("compress/mlx5: support partial transformation")
Cc: rzidane@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
 drivers/compress/mlx5/mlx5_compress.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index c0a861e5e4..d38f247216 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -243,8 +243,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 		mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
 	qp_attr.num_of_receive_wqes = 0;
 	qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n);
-	qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp
-			&& priv->mmo_dma_qp;
+	qp_attr.mmo = priv->mmo_decomp_qp || priv->mmo_comp_qp ||
+		      priv->mmo_dma_qp;
 	ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp,
 					qp_attr.num_of_send_wqbbs *
 					MLX5_WQE_SIZE, &qp_attr, socket_id);
-- 
2.25.1

[PATCH v2 1/8] compress/mlx5: fix decompress xform validation

[Michael Baum]

In xform creation, it first validate the xform according the
capabilities.

One of validations verifies that given "hash_algo" is
"RTE_COMP_HASH_ALGO_NONE" for both compress and decompress xform
objects.
However, the validation for decompress checks it again for compress
xform object.

This patch changes it to verify decompress xform object.

Fixes: 2efd26544554 ("compress/mlx5: support partial transformation")
Cc: rzidane@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
 drivers/compress/mlx5/mlx5_compress.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 459e4b5e8a..cadff83f27 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -313,7 +313,7 @@ mlx5_compress_xform_create(struct rte_compressdev *dev,
 			DRV_LOG(ERR, "Not enough capabilities to support decompress operation, maybe old FW/OFED version?");
 			return -ENOTSUP;
 		}
-		if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {
+		if (xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {
 			DRV_LOG(ERR, "SHA is not supported.");
 			return -ENOTSUP;
 		}
-- 
2.25.1

[PATCH v2 2/8] compress/mlx5: fix wrong output Adler-32 checksum offset

[Michael Baum]

After de/compress dequeue, the output checksum is copied into the op
structure. The "output_checksum" field in op structure is "uint64_t"
type, and the 32-bit checksums (CRC32, Adler-32) are copied into the
lower 32 bits.

When both CRC32 and Adler-32 are configured, CRC32 is copied into the
lower 32 bits and Adler-32 into the upper 32 bits.
However, in mlx5 PMD Adler-32 without CRC, is mistakenly copied into the
upper 32 bits.

This patch updates Adler-32 output checksun to be copied into the
lower 32 bits.

Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions")
Cc: matan@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
 drivers/compress/mlx5/mlx5_compress.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index cadff83f27..c46fb4eb89 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -633,7 +633,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 				break;
 			case RTE_COMP_CHECKSUM_ADLER32:
 				op->output_chksum = (uint64_t)rte_be_to_cpu_32
-					    (opaq[idx].adler32) << 32;
+						    (opaq[idx].adler32);
 				break;
 			case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 				op->output_chksum = (uint64_t)rte_be_to_cpu_32
-- 
2.25.1

[PATCH v2 3/8] compress/mlx5: fix QP setup for partial transformations

[Michael Baum]

The mlx5_compress_qp_setup() function creates QP for compress,
decompress and DMA. Thus, the MMO flag is turned on only when all
operations are supported.

However, since partial transformations have been allowed, it should be
turn on for part of them.

This patch removes the compress MMO support requirement.

Fixes: 2efd26544554 ("compress/mlx5: support partial transformation")
Cc: rzidane@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
 drivers/compress/mlx5/mlx5_compress.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index c46fb4eb89..c4bf62ed41 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -243,8 +243,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 		mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
 	qp_attr.num_of_receive_wqes = 0;
 	qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n);
-	qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp
-			&& priv->mmo_dma_qp;
+	qp_attr.mmo = priv->mmo_decomp_qp || priv->mmo_comp_qp ||
+		      priv->mmo_dma_qp;
 	ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp,
 					qp_attr.num_of_send_wqbbs *
 					MLX5_WQE_SIZE, &qp_attr, socket_id);
-- 
2.25.1

[PATCH v3 1/8] compress/mlx5: fix decompress xform validation

[Michael Baum]

In xform creation, it first validate the xform according the
capabilities.

One of validations verifies that given "hash_algo" is
"RTE_COMP_HASH_ALGO_NONE" for both compress and decompress xform
objects.
However, the validation for decompress checks it again for compress
xform object.

This patch changes it to verify decompress xform object.

Fixes: 2efd26544554 ("compress/mlx5: support partial transformation")
Cc: rzidane@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/compress/mlx5/mlx5_compress.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 430f769d41..06d1ff5b95 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -313,7 +313,7 @@ mlx5_compress_xform_create(struct rte_compressdev *dev,
 			DRV_LOG(ERR, "Not enough capabilities to support decompress operation, maybe old FW/OFED version?");
 			return -ENOTSUP;
 		}
-		if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {
+		if (xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {
 			DRV_LOG(ERR, "SHA is not supported.");
 			return -ENOTSUP;
 		}
-- 
2.25.1

[PATCH v3 2/8] compress/mlx5: fix wrong output Adler-32 checksum offset

[Michael Baum]

After de/compress dequeue, the output checksum is copied into the op
structure. The "output_checksum" field in op structure is "uint64_t"
type, and the 32-bit checksums (CRC32, Adler-32) are copied into the
lower 32 bits.

When both CRC32 and Adler-32 are configured, CRC32 is copied into the
lower 32 bits and Adler-32 into the upper 32 bits.
However, in mlx5 PMD Adler-32 without CRC, is mistakenly copied into the
upper 32 bits.

This patch updates Adler-32 output checksun to be copied into the
lower 32 bits.

Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions")
Cc: matan@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/compress/mlx5/mlx5_compress.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 06d1ff5b95..82088a7b8c 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -633,7 +633,7 @@ mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 				break;
 			case RTE_COMP_CHECKSUM_ADLER32:
 				op->output_chksum = (uint64_t)rte_be_to_cpu_32
-					    (opaq[idx].adler32) << 32;
+						    (opaq[idx].adler32);
 				break;
 			case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 				op->output_chksum = (uint64_t)rte_be_to_cpu_32
-- 
2.25.1

[PATCH v3 3/8] compress/mlx5: fix QP setup for partial transformations

[Michael Baum]

The mlx5_compress_qp_setup() function creates QP for compress,
decompress and DMA. Thus, the MMO flag is turned on only when all
operations are supported.

However, since partial transformations have been allowed, it should be
turn on for part of them.

This patch removes the compress MMO support requirement.

Fixes: 2efd26544554 ("compress/mlx5: support partial transformation")
Cc: rzidane@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/compress/mlx5/mlx5_compress.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 82088a7b8c..6882bcf6d1 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -243,8 +243,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 		mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
 	qp_attr.num_of_receive_wqes = 0;
 	qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n);
-	qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp
-			&& priv->mmo_dma_qp;
+	qp_attr.mmo = priv->mmo_decomp_qp || priv->mmo_comp_qp ||
+		      priv->mmo_dma_qp;
 	ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp,
 					qp_attr.num_of_send_wqbbs *
 					MLX5_WQE_SIZE, &qp_attr, socket_id);
-- 
2.25.1