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Mon, 20 Feb 2023 23:08:06 -0800 From: Michael Baum To: CC: Matan Azrad , Akhil Goyal , "Thomas Monjalon" , , Subject: [PATCH v3 3/8] compress/mlx5: fix QP setup for partial transformations Date: Tue, 21 Feb 2023 09:07:51 +0200 Message-ID: <20230221070756.3070819-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221070756.3070819-1-michaelba@nvidia.com> References: <20230202162537.1067595-1-michaelba@nvidia.com> <20230221070756.3070819-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT044:EE_|BL1PR12MB5972:EE_ X-MS-Office365-Filtering-Correlation-Id: d628dd55-72d7-4794-03d6-08db13da69c8 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ss6Sa+IR9AHBRcHsfStyAhSyJlqviA6guhYGoI5Emxj8dsHDPkCXNrGxEM2+pssOiX/ks+N++kE9jT7W1uLhxv0BZG6eSi0RmYzynccGrLwgvYwOuo203i/7BNPYbrnlO9yM/ssPTu0Z/zFS4DNpbm99JR8e8GUqG86mkdT3ci3tnTY2DNp/zpVOnQiSbvO+gXTfWclhA1ZAb096ql/dS80eR88HUNX3zpUTlxdjVSeRbwGeOO8ft8VFuMXqBxSw8lOCWjGDQBKphxxqkfQFwSF11E49zCAtr5oTgXRNFEKdx8AG8LofdvsJIjcQNEMwBIAqa1VpB5LrKLSsbwGmESr02jMXgFvxLL2orOYI2SHCWs4gR2CnBARySYi6btWekMm2CsaYKE2PYyjueF45kYf+fLdf2CwuDefsSFEsUX35lsZNgcTSQ6STEfob/Lo20+vEngmeuqj9fguVepeRzHa5/UQevX39OYvl5UAunfJCR4HXVF6JhPw8U/A14Y863LkszgLOR2C9D/cYYN8WZvgK3A1Sg1AFOQfZ1MZ1/UU0SGcrlUnrdsqWFsMPgk85qRqymmUcRyROdSqg4iGCRdVAz1YrWEnNa17UDWJ2Xtc8uBrKEk+1Lyva34Tdaeo769oTWW1Ee0YQ6M8p8QegnbR18PAcqhqmR7CuzOK5Y7zyCqVBneT0iMhpm4iQUDP0/zfzCGhxQJdfLVanYpfkTw== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(346002)(376002)(396003)(136003)(39860400002)(451199018)(36840700001)(40470700004)(46966006)(83380400001)(7696005)(2906002)(47076005)(336012)(426003)(2616005)(478600001)(36860700001)(5660300002)(55016003)(7636003)(82740400003)(4326008)(8936002)(186003)(26005)(1076003)(6916009)(8676002)(316002)(54906003)(356005)(40460700003)(6286002)(6666004)(40480700001)(82310400005)(70586007)(41300700001)(70206006)(86362001)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Feb 2023 07:08:19.9383 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d628dd55-72d7-4794-03d6-08db13da69c8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5972 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org The mlx5_compress_qp_setup() function creates QP for compress, decompress and DMA. Thus, the MMO flag is turned on only when all operations are supported. However, since partial transformations have been allowed, it should be turn on for part of them. This patch removes the compress MMO support requirement. Fixes: 2efd26544554 ("compress/mlx5: support partial transformation") Cc: rzidane@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/compress/mlx5/mlx5_compress.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 82088a7b8c..6882bcf6d1 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -243,8 +243,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format); qp_attr.num_of_receive_wqes = 0; qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n); - qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp - && priv->mmo_dma_qp; + qp_attr.mmo = priv->mmo_decomp_qp || priv->mmo_comp_qp || + priv->mmo_dma_qp; ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, qp_attr.num_of_send_wqbbs * MLX5_WQE_SIZE, &qp_attr, socket_id); -- 2.25.1