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From: Gerry Gribbon <ggribbon@nvidia.com>
To: <dev@dpdk.org>
CC: <stable@dpdk.org>, Ori Kam <orika@nvidia.com>
Subject: [PATCH] regex/mlx5: correct value written to doorbell db rec
Date: Tue, 21 Feb 2023 07:49:57 +0000
Message-ID: <20230221074958.1486157-1-ggribbon@nvidia.com>
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Errors-To: stable-bounces@dpdk.org
We were writing a value that should represent the number of items to be
processed by hardware. The value being written was off by 1 (N*4)+3;
The value should be (N*4) + 4 simplified to (N+1)*4
Fixes: 5dfa003db53f ("common/mlx5: fix post doorbell barrier")
Cc: stable@dpdk.org
Signed-off-by: Gerry Gribbon <ggribbon@nvidia.com>
---
drivers/regex/mlx5/mlx5_regex_fastpath.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c
index 143c7d7cdf..822370be83 100644
--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c
+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c
@@ -211,8 +211,8 @@ send_doorbell(struct mlx5_regex_priv *priv, struct mlx5_regex_hw_qp *qp)
(MLX5_SEND_WQE_BB << (priv->has_umr ? 2 : 0)) +
(priv->has_umr ? MLX5_REGEX_UMR_WQE_SIZE : 0);
uint8_t *wqe = (uint8_t *)(uintptr_t)qp->qp_obj.wqes + wqe_offset;
- uint32_t actual_pi = (priv->has_umr ? (qp->db_pi * 4 + 3) : qp->db_pi) &
- MLX5_REGEX_MAX_WQE_INDEX;
+ uint32_t actual_pi = (priv->has_umr ? ((1 + qp->db_pi) * 4) : qp->db_pi)
+ & MLX5_REGEX_MAX_WQE_INDEX;
/* Or the fm_ce_se instead of set, avoid the fence be cleared. */
((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se |= MLX5_WQE_CTRL_CQ_UPDATE;
--
2.25.1