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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS1PEPF0000E643.mail.protection.outlook.com (10.167.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6156.12 via Frontend Transport; Sat, 25 Feb 2023 20:19:01 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sat, 25 Feb 2023 12:18:50 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sat, 25 Feb 2023 12:18:48 -0800 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko CC: , , Ori Kam Subject: [PATCH 1/2] net/mlx5: fix egress group translation in HWS Date: Sat, 25 Feb 2023 20:18:09 +0000 Message-ID: <20230225201810.10838-2-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230225201810.10838-1-dsosnowski@nvidia.com> References: <20230225201810.10838-1-dsosnowski@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E643:EE_|CH0PR12MB5027:EE_ X-MS-Office365-Filtering-Correlation-Id: 840747f6-85cd-4d08-3331-08db176d8891 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2023 20:19:01.1586 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 840747f6-85cd-4d08-3331-08db176d8891 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E643.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5027 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org With HW Steering enabled creating egress template tables and egress flow rules on E-Switch setups is allowed. To enable it, PMD creates a set of default egress flow rules responsible for: - Storing representor ID (vport tag is used) in HW register. This is used for traffic source identification. - Copying software metadata to proper HW register to allow preserving metadata across domains. Structure of these flow rules and whether they are inserted depend on the device configuration. There are the following cases: 1. repr_matching=1 and dv_xmeta_en=4 - An egress flow rule in group 0 is created for each Tx queue; - Flow rule matching SQ number - fills unused REG_C_0 bits with vport tag, copies REG_A to REG_C_1 and jumps to group 1. 2. repr_matching=1 and dv_xmeta_en=0 - An egress flow rule in group 0 is created for each Tx queue; - Flow rule matching SQ number - fills unused REG_C_0 bits with vport tag and jumps to group 1. 3. repr_matching=0 and dv_xmeta_en=4 - A single egress flow rule in group 0 is created; - Flow rule matches all E-Switch manager TX traffic, copies REG_A to REG_C and jumps to group 1. 4. repr_matching=0 and dv_xmeta_en=0 - no default flow rules are added. When default egress flow rules are required, they are inserted in group 0 and this group is reserved for PMD purposes. User created template tables must be created in higher groups. As a result, on template table creation PMD is translating the provided group (incrementing it in that case). Before this patch, a condition used to check if translation of egress flow group is needed was incorrect. It did not allow translation if both representor matching AND extended metadata mode were enabled. This patch fixes this condition - translation is allowed if and only if representor matching OR extended metadata mode is enabled. Fixes: 483181f7b6dd ("net/mlx5: support device control of representor matching") Cc: stable@dpdk.org Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow_hw.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index a9c7045a3e..d3d86fe24d 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3260,14 +3260,18 @@ flow_hw_translate_group(struct rte_eth_dev *dev, "group index not supported"); *table_group = group + 1; } else if (config->dv_esw_en && - !(config->repr_matching && config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) && + (config->repr_matching || config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) && cfg->external && flow_attr->egress) { /* - * On E-Switch setups, egress group translation is not done if and only if - * representor matching is disabled and legacy metadata mode is selected. - * In all other cases, egree group 0 is reserved for representor tagging flows - * and metadata copy flows. + * On E-Switch setups, default egress flow rules are inserted to allow + * representor matching and/or preserving metadata across steering domains. + * These flow rules are inserted in group 0 and this group is reserved by PMD + * for these purposes. + * + * As a result, if representor matching or extended metadata mode is enabled, + * group provided by the user must be incremented to avoid inserting flow rules + * in group 0. */ if (group > MLX5_HW_MAX_EGRESS_GROUP) return rte_flow_error_set(error, EINVAL, -- 2.25.1