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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00010206.mail.protection.outlook.com (10.167.241.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6156.12 via Frontend Transport; Mon, 27 Feb 2023 07:14:47 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sun, 26 Feb 2023 23:14:29 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Sun, 26 Feb 2023 23:14:26 -0800 From: Xueming Li To: Viacheslav Ovsiienko CC: dpdk stable Subject: patch 'net/mlx5: fix read device clock in real time mode' has been queued to stable release 22.11.2 Date: Mon, 27 Feb 2023 15:00:33 +0800 Message-ID: <20230227070107.15664-125-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230227070107.15664-1-xuemingl@nvidia.com> References: <20230227062349.13764-1-xuemingl@nvidia.com> <20230227070107.15664-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00010206:EE_|SA3PR12MB8812:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a4221f0-f557-4e9f-638c-08db18924f0c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230025)(4636009)(39860400002)(346002)(396003)(136003)(376002)(451199018)(36840700001)(40470700004)(46966006)(2906002)(1076003)(5660300002)(6862004)(8936002)(36756003)(30864003)(41300700001)(40460700003)(70206006)(70586007)(55016003)(316002)(86362001)(40480700001)(37006003)(6636002)(966005)(7696005)(4326008)(8676002)(478600001)(356005)(82740400003)(7636003)(6666004)(36860700001)(82310400005)(53546011)(26005)(186003)(2616005)(336012)(16526019)(6286002)(426003)(47076005)(83380400001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2023 07:14:47.1528 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a4221f0-f557-4e9f-638c-08db18924f0c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00010206.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8812 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 03/01/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=394ba3cfc4fdd2cee49902603983d58849a8e9e1 Thanks. Xueming Li --- >From 394ba3cfc4fdd2cee49902603983d58849a8e9e1 Mon Sep 17 00:00:00 2001 From: Viacheslav Ovsiienko Date: Tue, 3 Jan 2023 13:11:45 +0200 Subject: [PATCH] net/mlx5: fix read device clock in real time mode Cc: Xueming Li [ upstream commit 9b31fc9007f9d706288b7d9852a86d2a5d0cd355 ] Since ConnectX-6DX the real time timestamp mode is supported. The rte_eth_read_clock() routine queries current timestamp value from the PMD. The mlx5 PMD has special infrastructure to schedule packet sending in real time mode which can be engaged with tx_pp devarg. This infrastructure provides the timestamp reading from the special queue CEQs directly from the host memory in user space, without involving kernel calls. The ConnectX-7 NIC has hardware capability to schedule packet sending without special infrastructure and tx_pp devarg can be omitted. If there is no tx_pp devarg specified the mlx5 uses kernel calls to query current timestamp value. The kernel can be completely unaware about engaged real time mode, also kernel might use its internal queue CQEs to get timestamps, that is neither precise nor reliable, inconsistent values might be returned, causing send scheduling malfunction. The HCA PCI BAR provides the real time direct reading from hardware. This patch maps PCI resource to the process address space on demand and allows reading the real time timestamp values from the NIC directly. Fixes: b94d93ca73803 ("net/mlx5: support reading device clock") Signed-off-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_common.h | 1 + drivers/common/mlx5/mlx5_prm.h | 5 +- drivers/common/mlx5/version.map | 1 + drivers/net/mlx5/linux/mlx5_ethdev_os.c | 68 +++++++++++++++++++++++ drivers/net/mlx5/mlx5.c | 6 +- drivers/net/mlx5/mlx5.h | 4 ++ drivers/net/mlx5/mlx5_txpp.c | 15 ++++- drivers/net/mlx5/windows/mlx5_ethdev_os.c | 30 ++++++++++ 8 files changed, 127 insertions(+), 3 deletions(-) diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index d6e91b5296..c7bd703497 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -221,6 +221,7 @@ check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n, * - 0 on success. * - Negative value and rte_errno is set otherwise. */ +__rte_internal int mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size); /* diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 3732fd0871..dab70b9469 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3043,6 +3043,7 @@ struct mlx5_ifc_health_buffer_bits { u8 ext_synd[0x10]; }; +/* HCA PCI BAR resource structure. */ struct mlx5_ifc_initial_seg_bits { u8 fw_rev_minor[0x10]; u8 fw_rev_major[0x10]; @@ -3070,7 +3071,9 @@ struct mlx5_ifc_initial_seg_bits { u8 clear_int[0x1]; u8 health_syndrome[0x8]; u8 health_counter[0x18]; - u8 reserved_8[0x17fc0]; + u8 reserved_8[0x160]; + u8 real_time[0x40]; + u8 reserved_9[0x17e20]; }; struct mlx5_ifc_create_cq_out_bits { diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index 4f72900519..03c8ce5593 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -14,6 +14,7 @@ INTERNAL { mlx5_dev_is_pci; mlx5_dev_is_vf_pci; + mlx5_dev_to_pci_str; mlx5_dev_mempool_unregister; mlx5_dev_mempool_subscribe; diff --git a/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/drivers/net/mlx5/linux/mlx5_ethdev_os.c index 72268c0c8a..f1ff6f49f9 100644 --- a/drivers/net/mlx5/linux/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/linux/mlx5_ethdev_os.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -1776,3 +1777,70 @@ exit: mlx5_free(sset_info); return ret; } + +/** + * Unmaps HCA PCI BAR from the current process address space. + * + * @param dev + * Pointer to Ethernet device structure. + */ +void mlx5_txpp_unmap_hca_bar(struct rte_eth_dev *dev) +{ + struct mlx5_proc_priv *ppriv = dev->process_private; + + if (ppriv && ppriv->hca_bar) { + rte_mem_unmap(ppriv->hca_bar, MLX5_ST_SZ_BYTES(initial_seg)); + ppriv->hca_bar = NULL; + } +} + +/** + * Maps HCA PCI BAR to the current process address space. + * Stores pointer in the process private structure allowing + * to read internal and real time counter directly from the HW. + * + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success and not NULL pointer to mapped area in process structure. + * negative otherwise and NULL pointer + */ +int mlx5_txpp_map_hca_bar(struct rte_eth_dev *dev) +{ + struct mlx5_proc_priv *ppriv = dev->process_private; + char pci_addr[PCI_PRI_STR_SIZE] = { 0 }; + void *base, *expected = NULL; + int fd, ret; + + if (!ppriv) { + rte_errno = ENOMEM; + return -rte_errno; + } + if (ppriv->hca_bar) + return 0; + ret = mlx5_dev_to_pci_str(dev->device, pci_addr, sizeof(pci_addr)); + if (ret < 0) + return -rte_errno; + /* Open PCI device resource 0 - HCA initialize segment */ + MKSTR(name, "/sys/bus/pci/devices/%s/resource0", pci_addr); + fd = open(name, O_RDWR | O_SYNC); + if (fd == -1) { + rte_errno = ENOTSUP; + return -ENOTSUP; + } + base = rte_mem_map(NULL, MLX5_ST_SZ_BYTES(initial_seg), + RTE_PROT_READ, RTE_MAP_SHARED, fd, 0); + close(fd); + if (!base) { + rte_errno = ENOTSUP; + return -ENOTSUP; + } + /* Check there is no concurrent mapping in other thread. */ + if (!__atomic_compare_exchange_n(&ppriv->hca_bar, &expected, + base, false, + __ATOMIC_RELAXED, __ATOMIC_RELAXED)) + rte_mem_unmap(base, MLX5_ST_SZ_BYTES(initial_seg)); + return 0; +} + diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 3ae35587b6..b8643cebdd 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1977,8 +1977,12 @@ mlx5_proc_priv_init(struct rte_eth_dev *dev) void mlx5_proc_priv_uninit(struct rte_eth_dev *dev) { - if (!dev->process_private) + struct mlx5_proc_priv *ppriv = dev->process_private; + + if (!ppriv) return; + if (ppriv->hca_bar) + mlx5_txpp_unmap_hca_bar(dev); mlx5_free(dev->process_private); dev->process_private = NULL; } diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 31982002ee..16b33e1548 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1463,6 +1463,8 @@ struct mlx5_dev_ctx_shared { * Caution, secondary process may rebuild the struct during port start. */ struct mlx5_proc_priv { + void *hca_bar; + /* Mapped HCA PCI BAR area. */ size_t uar_table_sz; /* Size of UAR register table. */ struct mlx5_uar_data uar_table[]; @@ -2163,6 +2165,8 @@ int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, struct rte_eth_xstat_name *xstats_names, unsigned int n, unsigned int n_used); void mlx5_txpp_interrupt_handler(void *cb_arg); +int mlx5_txpp_map_hca_bar(struct rte_eth_dev *dev); +void mlx5_txpp_unmap_hca_bar(struct rte_eth_dev *dev); /* mlx5_rxtx.c */ diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c index f853a67f58..63d98dbde9 100644 --- a/drivers/net/mlx5/mlx5_txpp.c +++ b/drivers/net/mlx5/mlx5_txpp.c @@ -969,6 +969,8 @@ mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp) { struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_dev_ctx_shared *sh = priv->sh; + struct mlx5_proc_priv *ppriv; + uint64_t ts; int ret; if (sh->txpp.refcnt) { @@ -979,7 +981,6 @@ mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp) rte_int128_t u128; struct mlx5_cqe_ts cts; } to; - uint64_t ts; mlx5_atomic_read_cqe((rte_int128_t *)&cqe->timestamp, &to.u128); if (to.cts.op_own >> 4) { @@ -994,6 +995,18 @@ mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp) *timestamp = ts; return 0; } + /* Check and try to map HCA PIC BAR to allow reading real time. */ + ppriv = dev->process_private; + if (ppriv && !ppriv->hca_bar && + sh->dev_cap.rt_timestamp && mlx5_dev_is_pci(dev->device)) + mlx5_txpp_map_hca_bar(dev); + /* Check if we can read timestamp directly from hardware. */ + if (ppriv && ppriv->hca_bar) { + ts = MLX5_GET64(initial_seg, ppriv->hca_bar, real_time); + ts = mlx5_txpp_convert_rx_ts(sh, ts); + *timestamp = ts; + return 0; + } /* Not supported in isolated mode - kernel does not see the CQEs. */ if (priv->isolated || rte_eal_process_type() != RTE_PROC_PRIMARY) return -ENOTSUP; diff --git a/drivers/net/mlx5/windows/mlx5_ethdev_os.c b/drivers/net/mlx5/windows/mlx5_ethdev_os.c index 88d8213f55..a31e1b5494 100644 --- a/drivers/net/mlx5/windows/mlx5_ethdev_os.c +++ b/drivers/net/mlx5/windows/mlx5_ethdev_os.c @@ -416,3 +416,33 @@ int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev) RTE_SET_USED(dev); return -ENOTSUP; } + +/** + * Unmaps HCA PCI BAR from the current process address space. + * + * @param dev + * Pointer to Ethernet device structure. + */ +void mlx5_txpp_unmap_hca_bar(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); +} + +/** + * Maps HCA PCI BAR to the current process address space. + * Stores pointer in the process private structure allowing + * to read internal and real time counter directly from the HW. + * + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success and not NULL pointer to mapped area in process structure. + * negative otherwise and NULL pointer + */ +int mlx5_txpp_map_hca_bar(struct rte_eth_dev *dev) +{ + RTE_SET_USED(dev); + rte_errno = ENOTSUP; + return -ENOTSUP; +} -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-02-27 14:08:44.917311900 +0800 +++ 0126-net-mlx5-fix-read-device-clock-in-real-time-mode.patch 2023-02-27 14:08:40.909237000 +0800 @@ -1 +1 @@ -From 9b31fc9007f9d706288b7d9852a86d2a5d0cd355 Mon Sep 17 00:00:00 2001 +From 394ba3cfc4fdd2cee49902603983d58849a8e9e1 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 9b31fc9007f9d706288b7d9852a86d2a5d0cd355 ] @@ -31 +33,0 @@ -Cc: stable@dpdk.org