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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF00010206.mail.protection.outlook.com (10.167.241.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6156.12 via Frontend Transport; Mon, 27 Feb 2023 07:15:08 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sun, 26 Feb 2023 23:14:59 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Sun, 26 Feb 2023 23:14:56 -0800 From: Xueming Li To: Alexander Kozyrev CC: Matan Azrad , dpdk stable Subject: patch 'net/mlx5: check compressed CQE opcode in vectorized Rx' has been queued to stable release 22.11.2 Date: Mon, 27 Feb 2023 15:00:37 +0800 Message-ID: <20230227070107.15664-129-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230227070107.15664-1-xuemingl@nvidia.com> References: <20230227062349.13764-1-xuemingl@nvidia.com> <20230227070107.15664-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00010206:EE_|DS0PR12MB7746:EE_ X-MS-Office365-Filtering-Correlation-Id: 532bd056-e4d2-48b8-0de6-08db18925bbe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230025)(4636009)(346002)(39860400002)(396003)(376002)(136003)(451199018)(36840700001)(40470700004)(46966006)(55016003)(36756003)(40480700001)(40460700003)(86362001)(478600001)(41300700001)(356005)(8936002)(4326008)(6862004)(2616005)(70206006)(7696005)(82310400005)(8676002)(70586007)(966005)(6636002)(316002)(54906003)(37006003)(5660300002)(6286002)(186003)(2906002)(36860700001)(83380400001)(7636003)(82740400003)(6666004)(47076005)(16526019)(26005)(53546011)(1076003)(426003)(336012); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2023 07:15:08.4499 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 532bd056-e4d2-48b8-0de6-08db18925bbe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00010206.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7746 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 03/01/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=4c6cddb596d67ed9c39617a5f8f557bd69d38f96 Thanks. Xueming Li --- >From 4c6cddb596d67ed9c39617a5f8f557bd69d38f96 Mon Sep 17 00:00:00 2001 From: Alexander Kozyrev Date: Fri, 27 Jan 2023 05:23:14 +0200 Subject: [PATCH] net/mlx5: check compressed CQE opcode in vectorized Rx Cc: Xueming Li [ upstream commit 1f903ebe2c05366aed6a453b6e7636945fc87285 ] The CQE opcode is never checked for a compressed CQE in the vectorized Rx burst routines. It is assumed that compressed CQEs are always valid and skipped error checking. This is obviously not the case and error CQEs may be compressed together as well. Need to check for the MLX5_CQE_RESP_ERR opcode and mark all the packets as bad ones in the compression session if it is there. Note that this issue is not applicable to the scalar Rx burst. Fixes: 6cb559d67b ("net/mlx5: add vectorized Rx/Tx burst for x86") Signed-off-by: Alexander Kozyrev Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 16 +++++++++++++--- drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 10 +++++++--- drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 9 ++++++--- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h index 683a8f9a6c..204d17a8f2 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h +++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h @@ -783,7 +783,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, { const uint16_t q_n = 1 << rxq->cqe_n; const uint16_t q_mask = q_n - 1; - unsigned int pos; + unsigned int pos, adj; uint64_t n = 0; uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; uint16_t nocmp_n = 0; @@ -866,7 +866,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, __vector unsigned char pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3; __vector unsigned char op_own, op_own_tmp1, op_own_tmp2; __vector unsigned char opcode, owner_mask, invalid_mask; - __vector unsigned char comp_mask; + __vector unsigned char comp_mask, mini_mask; __vector unsigned char mask; #ifdef MLX5_PMD_SOFT_COUNTERS const __vector unsigned char lower_half = { @@ -1174,6 +1174,16 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, (__vector unsigned long)mask); /* D.3 check error in opcode. */ + adj = (comp_idx != MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n); + mask = (__vector unsigned char)(__vector unsigned long){ + (adj * sizeof(uint16_t) * 8), 0}; + lshift = vec_splat((__vector unsigned long)mask, 0); + shmask = vec_cmpgt(shmax, lshift); + mini_mask = (__vector unsigned char) + vec_sl((__vector unsigned long)invalid_mask, lshift); + mini_mask = (__vector unsigned char) + vec_sel((__vector unsigned long)shmask, + (__vector unsigned long)mini_mask, shmask); opcode = (__vector unsigned char) vec_cmpeq((__vector unsigned int)resp_err_check, (__vector unsigned int)opcode); @@ -1182,7 +1192,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, (__vector unsigned int)zero); opcode = (__vector unsigned char) vec_andc((__vector unsigned long)opcode, - (__vector unsigned long)invalid_mask); + (__vector unsigned long)mini_mask); /* D.4 mark if any error is set */ *err |= ((__vector unsigned long)opcode)[0]; diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h index f7bbde4e0e..41b9cf5444 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h +++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h @@ -524,7 +524,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, { const uint16_t q_n = 1 << rxq->cqe_n; const uint16_t q_mask = q_n - 1; - unsigned int pos; + unsigned int pos, adj; uint64_t n = 0; uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; uint16_t nocmp_n = 0; @@ -616,7 +616,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, pos += MLX5_VPMD_DESCS_PER_LOOP) { uint16x4_t op_own; uint16x4_t opcode, owner_mask, invalid_mask; - uint16x4_t comp_mask; + uint16x4_t comp_mask, mini_mask; uint16x4_t mask; uint16x4_t byte_cnt; uint32x4_t ptype_info, flow_tag; @@ -780,8 +780,12 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, -1UL >> (n * sizeof(uint16_t) * 8) : 0); invalid_mask = vorr_u16(invalid_mask, mask); /* D.3 check error in opcode. */ + adj = (comp_idx != MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n); + mask = vcreate_u16(adj ? + -1UL >> ((n + 1) * sizeof(uint16_t) * 8) : -1UL); + mini_mask = vand_u16(invalid_mask, mask); opcode = vceq_u16(resp_err_check, opcode); - opcode = vbic_u16(opcode, invalid_mask); + opcode = vbic_u16(opcode, mini_mask); /* D.4 mark if any error is set */ *err |= vget_lane_u64(vreinterpret_u64_u16(opcode), 0); /* C.4 fill in mbuf - rearm_data and packet_type. */ diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h index 185d2695db..ab69af0c55 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h +++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h @@ -523,7 +523,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, { const uint16_t q_n = 1 << rxq->cqe_n; const uint16_t q_mask = q_n - 1; - unsigned int pos; + unsigned int pos, adj; uint64_t n = 0; uint64_t comp_idx = MLX5_VPMD_DESCS_PER_LOOP; uint16_t nocmp_n = 0; @@ -591,7 +591,7 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3; __m128i op_own, op_own_tmp1, op_own_tmp2; __m128i opcode, owner_mask, invalid_mask; - __m128i comp_mask; + __m128i comp_mask, mini_mask; __m128i mask; #ifdef MLX5_PMD_SOFT_COUNTERS __m128i byte_cnt; @@ -729,9 +729,12 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq, mask = _mm_sll_epi64(ones, mask); invalid_mask = _mm_or_si128(invalid_mask, mask); /* D.3 check error in opcode. */ + adj = (comp_idx != MLX5_VPMD_DESCS_PER_LOOP && comp_idx == n); + mask = _mm_set_epi64x(0, adj * sizeof(uint16_t) * 8); + mini_mask = _mm_sll_epi64(invalid_mask, mask); opcode = _mm_cmpeq_epi32(resp_err_check, opcode); opcode = _mm_packs_epi32(opcode, zero); - opcode = _mm_andnot_si128(invalid_mask, opcode); + opcode = _mm_andnot_si128(mini_mask, opcode); /* D.4 mark if any error is set */ *err |= _mm_cvtsi128_si64(opcode); /* D.5 fill in mbuf - rearm_data and packet_type. */ -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-02-27 14:08:45.045696900 +0800 +++ 0130-net-mlx5-check-compressed-CQE-opcode-in-vectorized-R.patch 2023-02-27 14:08:40.909237000 +0800 @@ -1 +1 @@ -From 1f903ebe2c05366aed6a453b6e7636945fc87285 Mon Sep 17 00:00:00 2001 +From 4c6cddb596d67ed9c39617a5f8f557bd69d38f96 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 1f903ebe2c05366aed6a453b6e7636945fc87285 ] @@ -18 +20,0 @@ -Cc: stable@dpdk.org