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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1NAM11FT022.mail.protection.outlook.com (10.13.175.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6156.16 via Frontend Transport; Mon, 27 Feb 2023 07:08:41 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sun, 26 Feb 2023 23:08:28 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Sun, 26 Feb 2023 23:08:26 -0800 From: Xueming Li To: Pavan Nikhilesh CC: dpdk stable Subject: patch 'event/cnxk: fix burst timer arm' has been queued to stable release 22.11.2 Date: Mon, 27 Feb 2023 14:59:35 +0800 Message-ID: <20230227070107.15664-67-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230227070107.15664-1-xuemingl@nvidia.com> References: <20230227062349.13764-1-xuemingl@nvidia.com> <20230227070107.15664-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT022:EE_|IA1PR12MB7589:EE_ X-MS-Office365-Filtering-Correlation-Id: f2f9a2ea-fe0b-4dcb-e9fa-08db18917529 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CAT:NONE; SFS:(13230025)(4636009)(39860400002)(396003)(376002)(346002)(136003)(451199018)(46966006)(40470700004)(36840700001)(8936002)(82310400005)(5660300002)(41300700001)(2906002)(36756003)(34020700004)(55016003)(40480700001)(7636003)(70206006)(4326008)(316002)(6916009)(966005)(7696005)(70586007)(36860700001)(83380400001)(86362001)(82740400003)(356005)(186003)(40460700003)(1076003)(6666004)(53546011)(47076005)(8676002)(336012)(426003)(2616005)(6286002)(16526019)(478600001)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Feb 2023 07:08:41.6500 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2f9a2ea-fe0b-4dcb-e9fa-08db18917529 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7589 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 03/01/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=903d4a18a1b6c53797015fa4488abdd2db059c26 Thanks. Xueming Li --- >From 903d4a18a1b6c53797015fa4488abdd2db059c26 Mon Sep 17 00:00:00 2001 From: Pavan Nikhilesh Date: Thu, 2 Feb 2023 13:40:24 +0530 Subject: [PATCH] event/cnxk: fix burst timer arm Cc: Xueming Li [ upstream commit d8ae421431312a966e924a3064fdc43a92b3264e ] Fix timer burst arm routine writing improper updates to the bucket. Fixes: 5f644e1bd14c ("event/cnxk: add timer arm timeout burst") Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cnxk_tim_worker.h | 81 ++++++++++++++-------------- 1 file changed, 42 insertions(+), 39 deletions(-) diff --git a/drivers/event/cnxk/cnxk_tim_worker.h b/drivers/event/cnxk/cnxk_tim_worker.h index eda84c6f31..6be31f6f9d 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.h +++ b/drivers/event/cnxk/cnxk_tim_worker.h @@ -270,7 +270,8 @@ __retry: } while (hbt_state & BIT_ULL(33)); #endif - if (!(hbt_state & BIT_ULL(34))) { + if (!(hbt_state & BIT_ULL(34)) || + !(hbt_state & GENMASK(31, 0))) { cnxk_tim_bkt_dec_lock(bkt); goto __retry; } @@ -352,7 +353,8 @@ __retry: } while (hbt_state & BIT_ULL(33)); #endif - if (!(hbt_state & BIT_ULL(34))) { + if (!(hbt_state & BIT_ULL(34)) || + !(hbt_state & GENMASK(31, 0))) { cnxk_tim_bkt_dec_lock(bkt); goto __retry; } @@ -449,10 +451,10 @@ cnxk_tim_add_entry_brst(struct cnxk_tim_ring *const tim_ring, struct cnxk_tim_ent *chunk = NULL; struct cnxk_tim_bkt *mirr_bkt; struct cnxk_tim_bkt *bkt; - uint16_t chunk_remainder; + int16_t chunk_remainder; uint16_t index = 0; uint64_t lock_sema; - int16_t rem, crem; + int16_t rem; uint8_t lock_cnt; __retry: @@ -460,31 +462,6 @@ __retry: /* Only one thread beyond this. */ lock_sema = cnxk_tim_bkt_inc_lock(bkt); - lock_cnt = (uint8_t)((lock_sema >> TIM_BUCKET_W1_S_LOCK) & - TIM_BUCKET_W1_M_LOCK); - - if (lock_cnt) { - cnxk_tim_bkt_dec_lock(bkt); -#ifdef RTE_ARCH_ARM64 - asm volatile(PLT_CPU_FEATURE_PREAMBLE - " ldxrb %w[lock_cnt], [%[lock]] \n" - " tst %w[lock_cnt], 255 \n" - " beq dne%= \n" - " sevl \n" - "rty%=: wfe \n" - " ldxrb %w[lock_cnt], [%[lock]] \n" - " tst %w[lock_cnt], 255 \n" - " bne rty%= \n" - "dne%=: \n" - : [lock_cnt] "=&r"(lock_cnt) - : [lock] "r"(&bkt->lock) - : "memory"); -#else - while (__atomic_load_n(&bkt->lock, __ATOMIC_RELAXED)) - ; -#endif - goto __retry; - } /* Bucket related checks. */ if (unlikely(cnxk_tim_bkt_get_hbt(lock_sema))) { @@ -509,21 +486,46 @@ __retry: } while (hbt_state & BIT_ULL(33)); #endif - if (!(hbt_state & BIT_ULL(34))) { + if (!(hbt_state & BIT_ULL(34)) || + !(hbt_state & GENMASK(31, 0))) { cnxk_tim_bkt_dec_lock(bkt); goto __retry; } } } + lock_cnt = (uint8_t)((lock_sema >> TIM_BUCKET_W1_S_LOCK) & + TIM_BUCKET_W1_M_LOCK); + if (lock_cnt) { + cnxk_tim_bkt_dec_lock(bkt); +#ifdef RTE_ARCH_ARM64 + asm volatile(PLT_CPU_FEATURE_PREAMBLE + " ldxrb %w[lock_cnt], [%[lock]] \n" + " tst %w[lock_cnt], 255 \n" + " beq dne%= \n" + " sevl \n" + "rty%=: wfe \n" + " ldxrb %w[lock_cnt], [%[lock]] \n" + " tst %w[lock_cnt], 255 \n" + " bne rty%= \n" + "dne%=: \n" + : [lock_cnt] "=&r"(lock_cnt) + : [lock] "r"(&bkt->lock) + : "memory"); +#else + while (__atomic_load_n(&bkt->lock, __ATOMIC_RELAXED)) + ; +#endif + goto __retry; + } + chunk_remainder = cnxk_tim_bkt_fetch_rem(lock_sema); rem = chunk_remainder - nb_timers; if (rem < 0) { - crem = tim_ring->nb_chunk_slots - chunk_remainder; - if (chunk_remainder && crem) { + if (chunk_remainder > 0) { chunk = ((struct cnxk_tim_ent *) mirr_bkt->current_chunk) + - crem; + tim_ring->nb_chunk_slots - chunk_remainder; index = cnxk_tim_cpy_wrk(index, chunk_remainder, chunk, tim, ents, bkt); @@ -537,18 +539,19 @@ __retry: chunk = cnxk_tim_insert_chunk(bkt, mirr_bkt, tim_ring); if (unlikely(chunk == NULL)) { - cnxk_tim_bkt_dec_lock(bkt); + cnxk_tim_bkt_dec_lock_relaxed(bkt); rte_errno = ENOMEM; tim[index]->state = RTE_EVENT_TIMER_ERROR; - return crem; + return index; } *(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0; mirr_bkt->current_chunk = (uintptr_t)chunk; - cnxk_tim_cpy_wrk(index, nb_timers, chunk, tim, ents, bkt); + index = cnxk_tim_cpy_wrk(index, nb_timers, chunk, tim, ents, + bkt) - + index; - rem = nb_timers - chunk_remainder; - cnxk_tim_bkt_set_rem(bkt, tim_ring->nb_chunk_slots - rem); - cnxk_tim_bkt_add_nent(bkt, rem); + cnxk_tim_bkt_set_rem(bkt, tim_ring->nb_chunk_slots - index); + cnxk_tim_bkt_add_nent(bkt, index); } else { chunk = (struct cnxk_tim_ent *)mirr_bkt->current_chunk; chunk += (tim_ring->nb_chunk_slots - chunk_remainder); -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-02-27 14:08:43.079835900 +0800 +++ 0068-event-cnxk-fix-burst-timer-arm.patch 2023-02-27 14:08:40.799237000 +0800 @@ -1 +1 @@ -From d8ae421431312a966e924a3064fdc43a92b3264e Mon Sep 17 00:00:00 2001 +From 903d4a18a1b6c53797015fa4488abdd2db059c26 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit d8ae421431312a966e924a3064fdc43a92b3264e ] @@ -9 +11,0 @@ -Cc: stable@dpdk.org @@ -17 +19 @@ -index 16909ef06d..5fa1acca90 100644 +index eda84c6f31..6be31f6f9d 100644 @@ -20 +22 @@ -@@ -272,7 +272,8 @@ __retry: +@@ -270,7 +270,8 @@ __retry: @@ -30 +32 @@ -@@ -354,7 +355,8 @@ __retry: +@@ -352,7 +353,8 @@ __retry: @@ -40 +42 @@ -@@ -451,10 +453,10 @@ cnxk_tim_add_entry_brst(struct cnxk_tim_ring *const tim_ring, +@@ -449,10 +451,10 @@ cnxk_tim_add_entry_brst(struct cnxk_tim_ring *const tim_ring, @@ -53 +55 @@ -@@ -462,31 +464,6 @@ __retry: +@@ -460,31 +462,6 @@ __retry: @@ -85 +87 @@ -@@ -511,21 +488,46 @@ __retry: +@@ -509,21 +486,46 @@ __retry: @@ -136 +138 @@ -@@ -539,18 +541,19 @@ __retry: +@@ -537,18 +539,19 @@ __retry: