* [PATCH 22.11] common/cnxk: fix second pass flow rule layer type
@ 2023-02-27 9:37 psatheesh
2023-04-08 12:47 ` Xueming(Steven) Li
0 siblings, 1 reply; 2+ messages in thread
From: psatheesh @ 2023-02-27 9:37 UTC (permalink / raw)
To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
Cc: stable, Satheesh Paul
From: Satheesh Paul <psatheesh@marvell.com>
When installing flow rule for second pass packets, set the
LA LTYPE to LA_CPT_HDR.
Fixes: 4968b362b639 ("common/cnxk: support CPT second pass flow rules")
Cc: stable@dpdk.org
[ upstream commit a0c837ad1fb5b6a8b10a284ffeb5f9e31bd8ff00 ]
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
---
drivers/common/cnxk/roc_npc_mcam.c | 39 +++++++++++++++++++++----
drivers/common/cnxk/roc_npc_mcam_dump.c | 6 ++--
drivers/common/cnxk/roc_npc_parse.c | 1 +
drivers/common/cnxk/roc_npc_priv.h | 1 +
4 files changed, 39 insertions(+), 8 deletions(-)
diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c
index a725cabc57..7e1599e606 100644
--- a/drivers/common/cnxk/roc_npc_mcam.c
+++ b/drivers/common/cnxk/roc_npc_mcam.c
@@ -551,6 +551,8 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,
struct idev_cfg *idev;
uint16_t pf_func = 0;
uint16_t ctr = ~(0);
+ uint32_t la_offset;
+ uint64_t mask;
int rc, idx;
int entry;
@@ -617,17 +619,42 @@ npc_mcam_alloc_and_write(struct npc *npc, struct roc_npc_flow *flow,
flow->npc_action &= ~(GENMASK(19, 4));
flow->npc_action |= (uint64_t)pf_func << 4;
- npc_mcam_set_channel(flow, req, inl_dev->channel,
- inl_dev->chan_mask, false);
+ npc_mcam_set_channel(flow, req, inl_dev->channel, inl_dev->chan_mask,
+ false);
} else if (npc->is_sdp_link) {
- npc_mcam_set_channel(flow, req, npc->sdp_channel,
- npc->sdp_channel_mask,
+ npc_mcam_set_channel(flow, req, npc->sdp_channel, npc->sdp_channel_mask,
pst->is_second_pass_rule);
} else {
- npc_mcam_set_channel(flow, req, npc->channel,
- (BIT_ULL(12) - 1),
+ npc_mcam_set_channel(flow, req, npc->channel, (BIT_ULL(12) - 1),
pst->is_second_pass_rule);
}
+ /*
+ * For second pass rule, set LA LTYPE to CPT_HDR.
+ * For all other rules, set LA LTYPE to match both 1st pass and 2nd pass ltypes.
+ */
+ if (pst->is_second_pass_rule || (!pst->is_second_pass_rule && pst->has_eth_type)) {
+ la_offset = __builtin_popcount(npc->keyx_supp_nmask[flow->nix_intf] &
+ ((1ULL << 9 /* LA offset */) - 1));
+ la_offset *= 4;
+
+ mask = ~((0xfULL << la_offset));
+ req->entry_data.kw[0] &= mask;
+ req->entry_data.kw_mask[0] &= mask;
+ flow->mcam_data[0] &= mask;
+ flow->mcam_mask[0] &= mask;
+ if (pst->is_second_pass_rule) {
+ req->entry_data.kw[0] |= ((uint64_t)NPC_LT_LA_CPT_HDR) << la_offset;
+ req->entry_data.kw_mask[0] |= (0xFULL << la_offset);
+ flow->mcam_data[0] |= ((uint64_t)NPC_LT_LA_CPT_HDR) << la_offset;
+ flow->mcam_mask[0] |= (0xFULL << la_offset);
+ } else {
+ /* Mask ltype ETHER (0x2) and CPT_HDR (0xa) */
+ req->entry_data.kw[0] |= (0x2ULL << la_offset);
+ req->entry_data.kw_mask[0] |= (0x7ULL << la_offset);
+ flow->mcam_data[0] |= (0x2ULL << la_offset);
+ flow->mcam_mask[0] |= (0x7ULL << la_offset);
+ }
+ }
} else {
uint16_t pf_func = (flow->npc_action >> 4) & 0xffff;
diff --git a/drivers/common/cnxk/roc_npc_mcam_dump.c b/drivers/common/cnxk/roc_npc_mcam_dump.c
index fe57811a84..cc1599ef33 100644
--- a/drivers/common/cnxk/roc_npc_mcam_dump.c
+++ b/drivers/common/cnxk/roc_npc_mcam_dump.c
@@ -69,8 +69,10 @@ static const char *const ltype_str[NPC_MAX_LID][NPC_MAX_LT] = {
[NPC_LID_LA][NPC_LT_LA_IH_NIX_ETHER] = "LA_IH_NIX_ETHER",
[NPC_LID_LA][NPC_LT_LA_HIGIG2_ETHER] = "LA_HIGIG2_ETHER",
[NPC_LID_LA][NPC_LT_LA_IH_NIX_HIGIG2_ETHER] = "LA_IH_NIX_HIGIG2_ETHER",
- [NPC_LID_LA][NPC_LT_LA_CUSTOM_PRE_L2_ETHER] =
- "NPC_LT_LA_CUSTOM_PRE_L2_ETHER",
+ [NPC_LID_LA][NPC_LT_LA_CUSTOM_L2_90B_ETHER] = "LA_CUSTOM_L2_90B_ETHER",
+ [NPC_LID_LA][NPC_LT_LA_CPT_HDR] = "LA_CPT_HDR",
+ [NPC_LID_LA][NPC_LT_LA_CUSTOM_L2_24B_ETHER] = "LA_CUSTOM_L2_24B_ETHER",
+ [NPC_LID_LA][NPC_LT_LA_CUSTOM_PRE_L2_ETHER] = "NPC_LT_LA_CUSTOM_PRE_L2_ETHER",
[NPC_LID_LB][0] = "NONE",
[NPC_LID_LB][NPC_LT_LB_CTAG] = "LB_CTAG",
[NPC_LID_LB][NPC_LT_LB_STAG_QINQ] = "LB_STAG_QINQ",
diff --git a/drivers/common/cnxk/roc_npc_parse.c b/drivers/common/cnxk/roc_npc_parse.c
index ff00c746d6..947e1ec53d 100644
--- a/drivers/common/cnxk/roc_npc_parse.c
+++ b/drivers/common/cnxk/roc_npc_parse.c
@@ -193,6 +193,7 @@ npc_parse_la(struct npc_parse_state *pst)
if (pst->pattern->type != ROC_NPC_ITEM_TYPE_ETH)
return 0;
+ pst->has_eth_type = true;
eth_item = pst->pattern->spec;
lid = NPC_LID_LA;
diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
index 1a597280d1..09a727b13e 100644
--- a/drivers/common/cnxk/roc_npc_priv.h
+++ b/drivers/common/cnxk/roc_npc_priv.h
@@ -196,6 +196,7 @@ struct npc_parse_state {
bool set_vlan_ltype_mask;
bool set_ipv6ext_ltype_mask;
bool is_second_pass_rule;
+ bool has_eth_type;
};
enum npc_kpu_parser_flag {
--
2.35.3
^ permalink raw reply [flat|nested] 2+ messages in thread
* RE: [PATCH 22.11] common/cnxk: fix second pass flow rule layer type
2023-02-27 9:37 [PATCH 22.11] common/cnxk: fix second pass flow rule layer type psatheesh
@ 2023-04-08 12:47 ` Xueming(Steven) Li
0 siblings, 0 replies; 2+ messages in thread
From: Xueming(Steven) Li @ 2023-04-08 12:47 UTC (permalink / raw)
To: psatheesh, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao
Cc: stable
Thanks for your support, patch queued.
Best Regards,
Xueming
> -----Original Message-----
> From: psatheesh@marvell.com <psatheesh@marvell.com>
> Sent: 2/27/2023 17:37
> To: Nithin Dabilpuram <ndabilpuram@marvell.com>; Kiran Kumar K
> <kirankumark@marvell.com>; Sunil Kumar Kori <skori@marvell.com>; Satha
> Rao <skoteshwar@marvell.com>
> Cc: stable@dpdk.org; Satheesh Paul <psatheesh@marvell.com>
> Subject: [PATCH 22.11] common/cnxk: fix second pass flow rule layer type
>
> From: Satheesh Paul <psatheesh@marvell.com>
>
> When installing flow rule for second pass packets, set the LA LTYPE to
> LA_CPT_HDR.
>
> Fixes: 4968b362b639 ("common/cnxk: support CPT second pass flow rules")
> Cc: stable@dpdk.org
>
> [ upstream commit a0c837ad1fb5b6a8b10a284ffeb5f9e31bd8ff00 ]
>
> Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
> ---
> drivers/common/cnxk/roc_npc_mcam.c | 39 +++++++++++++++++++++----
> drivers/common/cnxk/roc_npc_mcam_dump.c | 6 ++--
> drivers/common/cnxk/roc_npc_parse.c | 1 +
> drivers/common/cnxk/roc_npc_priv.h | 1 +
> 4 files changed, 39 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_npc_mcam.c
> b/drivers/common/cnxk/roc_npc_mcam.c
> index a725cabc57..7e1599e606 100644
> --- a/drivers/common/cnxk/roc_npc_mcam.c
> +++ b/drivers/common/cnxk/roc_npc_mcam.c
> @@ -551,6 +551,8 @@ npc_mcam_alloc_and_write(struct npc *npc, struct
> roc_npc_flow *flow,
> struct idev_cfg *idev;
> uint16_t pf_func = 0;
> uint16_t ctr = ~(0);
> + uint32_t la_offset;
> + uint64_t mask;
> int rc, idx;
> int entry;
>
> @@ -617,17 +619,42 @@ npc_mcam_alloc_and_write(struct npc *npc, struct
> roc_npc_flow *flow,
> flow->npc_action &= ~(GENMASK(19, 4));
> flow->npc_action |= (uint64_t)pf_func << 4;
>
> - npc_mcam_set_channel(flow, req, inl_dev->channel,
> - inl_dev->chan_mask, false);
> + npc_mcam_set_channel(flow, req, inl_dev->channel,
> inl_dev->chan_mask,
> + false);
> } else if (npc->is_sdp_link) {
> - npc_mcam_set_channel(flow, req, npc->sdp_channel,
> - npc->sdp_channel_mask,
> + npc_mcam_set_channel(flow, req, npc->sdp_channel,
> +npc->sdp_channel_mask,
> pst->is_second_pass_rule);
> } else {
> - npc_mcam_set_channel(flow, req, npc->channel,
> - (BIT_ULL(12) - 1),
> + npc_mcam_set_channel(flow, req, npc->channel,
> (BIT_ULL(12) - 1),
> pst->is_second_pass_rule);
> }
> + /*
> + * For second pass rule, set LA LTYPE to CPT_HDR.
> + * For all other rules, set LA LTYPE to match both 1st pass and
> 2nd pass ltypes.
> + */
> + if (pst->is_second_pass_rule || (!pst->is_second_pass_rule
> && pst->has_eth_type)) {
> + la_offset = __builtin_popcount(npc-
> >keyx_supp_nmask[flow->nix_intf] &
> + ((1ULL << 9 /* LA offset */)
> - 1));
> + la_offset *= 4;
> +
> + mask = ~((0xfULL << la_offset));
> + req->entry_data.kw[0] &= mask;
> + req->entry_data.kw_mask[0] &= mask;
> + flow->mcam_data[0] &= mask;
> + flow->mcam_mask[0] &= mask;
> + if (pst->is_second_pass_rule) {
> + req->entry_data.kw[0] |=
> ((uint64_t)NPC_LT_LA_CPT_HDR) << la_offset;
> + req->entry_data.kw_mask[0] |= (0xFULL <<
> la_offset);
> + flow->mcam_data[0] |=
> ((uint64_t)NPC_LT_LA_CPT_HDR) << la_offset;
> + flow->mcam_mask[0] |= (0xFULL << la_offset);
> + } else {
> + /* Mask ltype ETHER (0x2) and CPT_HDR (0xa)
> */
> + req->entry_data.kw[0] |= (0x2ULL <<
> la_offset);
> + req->entry_data.kw_mask[0] |= (0x7ULL <<
> la_offset);
> + flow->mcam_data[0] |= (0x2ULL << la_offset);
> + flow->mcam_mask[0] |= (0x7ULL << la_offset);
> + }
> + }
> } else {
> uint16_t pf_func = (flow->npc_action >> 4) & 0xffff;
>
> diff --git a/drivers/common/cnxk/roc_npc_mcam_dump.c
> b/drivers/common/cnxk/roc_npc_mcam_dump.c
> index fe57811a84..cc1599ef33 100644
> --- a/drivers/common/cnxk/roc_npc_mcam_dump.c
> +++ b/drivers/common/cnxk/roc_npc_mcam_dump.c
> @@ -69,8 +69,10 @@ static const char *const
> ltype_str[NPC_MAX_LID][NPC_MAX_LT] = {
> [NPC_LID_LA][NPC_LT_LA_IH_NIX_ETHER] = "LA_IH_NIX_ETHER",
> [NPC_LID_LA][NPC_LT_LA_HIGIG2_ETHER] = "LA_HIGIG2_ETHER",
> [NPC_LID_LA][NPC_LT_LA_IH_NIX_HIGIG2_ETHER] =
> "LA_IH_NIX_HIGIG2_ETHER",
> - [NPC_LID_LA][NPC_LT_LA_CUSTOM_PRE_L2_ETHER] =
> - "NPC_LT_LA_CUSTOM_PRE_L2_ETHER",
> + [NPC_LID_LA][NPC_LT_LA_CUSTOM_L2_90B_ETHER] =
> "LA_CUSTOM_L2_90B_ETHER",
> + [NPC_LID_LA][NPC_LT_LA_CPT_HDR] = "LA_CPT_HDR",
> + [NPC_LID_LA][NPC_LT_LA_CUSTOM_L2_24B_ETHER] =
> "LA_CUSTOM_L2_24B_ETHER",
> + [NPC_LID_LA][NPC_LT_LA_CUSTOM_PRE_L2_ETHER] =
> +"NPC_LT_LA_CUSTOM_PRE_L2_ETHER",
> [NPC_LID_LB][0] = "NONE",
> [NPC_LID_LB][NPC_LT_LB_CTAG] = "LB_CTAG",
> [NPC_LID_LB][NPC_LT_LB_STAG_QINQ] = "LB_STAG_QINQ", diff --git
> a/drivers/common/cnxk/roc_npc_parse.c
> b/drivers/common/cnxk/roc_npc_parse.c
> index ff00c746d6..947e1ec53d 100644
> --- a/drivers/common/cnxk/roc_npc_parse.c
> +++ b/drivers/common/cnxk/roc_npc_parse.c
> @@ -193,6 +193,7 @@ npc_parse_la(struct npc_parse_state *pst)
> if (pst->pattern->type != ROC_NPC_ITEM_TYPE_ETH)
> return 0;
>
> + pst->has_eth_type = true;
> eth_item = pst->pattern->spec;
>
> lid = NPC_LID_LA;
> diff --git a/drivers/common/cnxk/roc_npc_priv.h
> b/drivers/common/cnxk/roc_npc_priv.h
> index 1a597280d1..09a727b13e 100644
> --- a/drivers/common/cnxk/roc_npc_priv.h
> +++ b/drivers/common/cnxk/roc_npc_priv.h
> @@ -196,6 +196,7 @@ struct npc_parse_state {
> bool set_vlan_ltype_mask;
> bool set_ipv6ext_ltype_mask;
> bool is_second_pass_rule;
> + bool has_eth_type;
> };
>
> enum npc_kpu_parser_flag {
> --
> 2.35.3
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-02-27 9:37 [PATCH 22.11] common/cnxk: fix second pass flow rule layer type psatheesh
2023-04-08 12:47 ` Xueming(Steven) Li
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