From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0134841DAC for ; Wed, 1 Mar 2023 14:59:24 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ED78341181; Wed, 1 Mar 2023 14:59:23 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id A1F2C4113C; Wed, 1 Mar 2023 14:59:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677679162; x=1709215162; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=/q49+3GzB46gIwqCFgrX54uVdSqTxbs5hppdvEdaxTs=; b=kJC46KCulM7ZtzmBmBr47G1uwWQViA0GuMU5/YmZmAWFRDQ3k3pAOwz3 E7wMIXrGkALTymzfsIoQ7OIHJDS4fcRaMrUvRpoWVvgqNSJh5I0ngCaF3 fptndIOJKQz8TxsBSHslwCxK65dhJ48Spcsx7hbLTxE8Sr8zQLkeG4RKD nAJhwNSeM9yfJgTlNWtj1auaCGJ/UbXXeuppMkUHe7GwTNNH8uTAW1VI/ FYucY72e9GYKigAMCXpC+yKN0yojfZOHc8YphQ6aXcsZzjpBvT1PQETZz klVQOD0vQ7Wsqf16tyq18bpX6h6aNE9sptLVZCp5B+G6qLGCYsW0D2ZXZ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="318212581" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="318212581" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 05:59:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="1003683238" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="1003683238" Received: from silpixa00400355.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.80]) by fmsmga005.fm.intel.com with ESMTP; 01 Mar 2023 05:59:18 -0800 From: Ciara Power To: Kai Ji Cc: dev@dpdk.org, Ciara Power , arkadiuszx.kusztal@intel.com, stable@dpdk.org Subject: [PATCH] crypto/qat: fix SM3 auth mode Date: Wed, 1 Mar 2023 13:59:15 +0000 Message-Id: <20230301135915.2184760-1-ciara.power@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org The SM3 auth mode is now set to 0 for QAT, to support plain hash only. This should also be added to the capabilities for GEN3 and GEN4. SM3 HMAC is not supported. Fixes: 75fd4bbc94ab ("crypto/qat: support SM3 hash algorithm") Cc: arkadiuszx.kusztal@intel.com Cc: stable@dpdk.org Signed-off-by: Ciara Power --- drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 3 +++ drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 3 +++ drivers/crypto/qat/qat_sym_session.c | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c index 5fa898dc8f..6013fed721 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c @@ -152,6 +152,9 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen3[] = { QAT_SYM_CIPHER_CAP(SM4_CTR, CAP_SET(block_size, 16), CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), + QAT_SYM_PLAIN_AUTH_CAP(SM3, + CAP_SET(block_size, 64), + CAP_RNG(digest_size, 32, 32, 0)), RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index b1e5fa9a82..b219a418ba 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -100,6 +100,9 @@ static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = { QAT_SYM_CIPHER_CAP(SM4_CTR, CAP_SET(block_size, 16), CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)), + QAT_SYM_PLAIN_AUTH_CAP(SM3, + CAP_SET(block_size, 64), + CAP_RNG(digest_size, 32, 32, 0)), RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() }; diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 466482d225..6ad6c7ee3a 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -697,7 +697,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, switch (auth_xform->algo) { case RTE_CRYPTO_AUTH_SM3: session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SM3; - session->auth_mode = ICP_QAT_HW_AUTH_MODE2; + session->auth_mode = ICP_QAT_HW_AUTH_MODE0; break; case RTE_CRYPTO_AUTH_SHA1: session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1; -- 2.25.1