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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT057.mail.protection.outlook.com (10.13.177.49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6298.26 via Frontend Transport; Sun, 9 Apr 2023 15:36:15 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Sun, 9 Apr 2023 08:36:05 -0700 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Sun, 9 Apr 2023 08:36:03 -0700 From: Xueming Li To: Dariusz Sosnowski CC: Ori Kam , Suanming Mou , "Matan Azrad" , dpdk stable Subject: patch 'net/mlx5: fix egress group translation in HWS' has been queued to stable release 22.11.2 Date: Sun, 9 Apr 2023 23:25:10 +0800 Message-ID: <20230409152529.5308-123-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230409152529.5308-1-xuemingl@nvidia.com> References: <20230227062349.13764-1-xuemingl@nvidia.com> <20230409152529.5308-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT057:EE_|SJ0PR12MB5488:EE_ X-MS-Office365-Filtering-Correlation-Id: f61a8083-574e-4bdf-cda5-08db391027fd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(346002)(136003)(39860400002)(376002)(396003)(451199021)(40470700004)(46966006)(36840700001)(86362001)(36756003)(37006003)(316002)(41300700001)(70586007)(70206006)(8676002)(4326008)(6636002)(966005)(7696005)(54906003)(478600001)(40480700001)(55016003)(82310400005)(6862004)(5660300002)(8936002)(2906002)(36860700001)(356005)(82740400003)(7636003)(16526019)(6286002)(186003)(53546011)(6666004)(1076003)(26005)(426003)(336012)(2616005)(47076005)(83380400001)(40460700003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2023 15:36:15.4230 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f61a8083-574e-4bdf-cda5-08db391027fd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5488 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 04/11/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging/commit/e10c2200535417041f96e9d7d403d6ee3ae6cb29 Thanks. Xueming Li --- >From e10c2200535417041f96e9d7d403d6ee3ae6cb29 Mon Sep 17 00:00:00 2001 From: Dariusz Sosnowski Date: Sat, 25 Feb 2023 20:18:09 +0000 Subject: [PATCH] net/mlx5: fix egress group translation in HWS Cc: Xueming Li [ upstream commit 4900c42e0cf035bb3326b46ac3fe615b490c64d7 ] With HW Steering enabled creating egress template tables and egress flow rules on E-Switch setups is allowed. To enable it, PMD creates a set of default egress flow rules responsible for: - Storing representor ID (vport tag is used) in HW register. This is used for traffic source identification. - Copying software metadata to proper HW register to allow preserving metadata across domains. Structure of these flow rules and whether they are inserted depend on the device configuration. There are the following cases: 1. repr_matching=1 and dv_xmeta_en=4 - An egress flow rule in group 0 is created for each Tx queue; - Flow rule matching SQ number - fills unused REG_C_0 bits with vport tag, copies REG_A to REG_C_1 and jumps to group 1. 2. repr_matching=1 and dv_xmeta_en=0 - An egress flow rule in group 0 is created for each Tx queue; - Flow rule matching SQ number - fills unused REG_C_0 bits with vport tag and jumps to group 1. 3. repr_matching=0 and dv_xmeta_en=4 - A single egress flow rule in group 0 is created; - Flow rule matches all E-Switch manager TX traffic, copies REG_A to REG_C and jumps to group 1. 4. repr_matching=0 and dv_xmeta_en=0 - no default flow rules are added. When default egress flow rules are required, they are inserted in group 0 and this group is reserved for PMD purposes. User created template tables must be created in higher groups. As a result, on template table creation PMD is translating the provided group (incrementing it in that case). Before this patch, a condition used to check if translation of egress flow group is needed was incorrect. It did not allow translation if both representor matching AND extended metadata mode were enabled. This patch fixes this condition - translation is allowed if and only if representor matching OR extended metadata mode is enabled. Fixes: 483181f7b6dd ("net/mlx5: support device control of representor matching") Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam Acked-by: Suanming Mou Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_flow_hw.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 2fe33bbef8..ead14a0530 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3252,14 +3252,18 @@ flow_hw_translate_group(struct rte_eth_dev *dev, "group index not supported"); *table_group = group + 1; } else if (config->dv_esw_en && - !(config->repr_matching && config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) && + (config->repr_matching || config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) && cfg->external && flow_attr->egress) { /* - * On E-Switch setups, egress group translation is not done if and only if - * representor matching is disabled and legacy metadata mode is selected. - * In all other cases, egree group 0 is reserved for representor tagging flows - * and metadata copy flows. + * On E-Switch setups, default egress flow rules are inserted to allow + * representor matching and/or preserving metadata across steering domains. + * These flow rules are inserted in group 0 and this group is reserved by PMD + * for these purposes. + * + * As a result, if representor matching or extended metadata mode is enabled, + * group provided by the user must be incremented to avoid inserting flow rules + * in group 0. */ if (group > MLX5_HW_MAX_EGRESS_GROUP) return rte_flow_error_set(error, EINVAL, -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-04-09 21:45:41.888447700 +0800 +++ 0122-net-mlx5-fix-egress-group-translation-in-HWS.patch 2023-04-09 21:45:38.789042200 +0800 @@ -1 +1 @@ -From 4900c42e0cf035bb3326b46ac3fe615b490c64d7 Mon Sep 17 00:00:00 2001 +From e10c2200535417041f96e9d7d403d6ee3ae6cb29 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 4900c42e0cf035bb3326b46ac3fe615b490c64d7 ] @@ -48 +50,0 @@ -Cc: stable@dpdk.org @@ -59 +61 @@ -index a3e211633d..a4328a9f50 100644 +index 2fe33bbef8..ead14a0530 100644 @@ -62 +64 @@ -@@ -3415,14 +3415,18 @@ flow_hw_translate_group(struct rte_eth_dev *dev, +@@ -3252,14 +3252,18 @@ flow_hw_translate_group(struct rte_eth_dev *dev,