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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT106.mail.protection.outlook.com (10.13.177.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6298.25 via Frontend Transport; Sun, 9 Apr 2023 15:33:18 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Sun, 9 Apr 2023 08:33:04 -0700 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Sun, 9 Apr 2023 08:33:03 -0700 From: Xueming Li To: Thomas Monjalon CC: Tyler Retzlaff , Tal Shnaiderman , dpdk stable Subject: patch 'net/mlx5: fix Windows build with MinGW GCC 12' has been queued to stable release 22.11.2 Date: Sun, 9 Apr 2023 23:24:36 +0800 Message-ID: <20230409152529.5308-89-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230409152529.5308-1-xuemingl@nvidia.com> References: <20230227062349.13764-1-xuemingl@nvidia.com> <20230409152529.5308-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT106:EE_|PH8PR12MB6676:EE_ X-MS-Office365-Filtering-Correlation-Id: 674ba8d3-9fe5-4130-7152-08db390fbecb X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(346002)(39860400002)(136003)(376002)(396003)(451199021)(36840700001)(40470700004)(46966006)(478600001)(7696005)(6666004)(54906003)(316002)(1076003)(26005)(53546011)(16526019)(6286002)(186003)(966005)(2906002)(70586007)(70206006)(8676002)(6916009)(4326008)(41300700001)(8936002)(5660300002)(82310400005)(356005)(82740400003)(7636003)(86362001)(55016003)(40480700001)(36756003)(40460700003)(47076005)(83380400001)(2616005)(426003)(336012)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2023 15:33:18.9166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 674ba8d3-9fe5-4130-7152-08db390fbecb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6676 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 04/11/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging/commit/f081724c6bf5431062257f4893e078876eb904c8 Thanks. Xueming Li --- >From f081724c6bf5431062257f4893e078876eb904c8 Mon Sep 17 00:00:00 2001 From: Thomas Monjalon Date: Thu, 2 Mar 2023 14:21:50 +0100 Subject: [PATCH] net/mlx5: fix Windows build with MinGW GCC 12 Cc: Xueming Li [ upstream commit 8ce24f0c8398b1129b64af83d49bf6fa8567c472 ] With recent changes in Meson and MinGW toolchain, the driver mlx5 was not able to compile on Linux for Windows. There were errors due to system detection, non-typed constants, constant going over int range forbidden in pedantic mode, and minimum-comparison of different types. Signed-off-by: Thomas Monjalon Acked-by: Tyler Retzlaff Acked-by: Tal Shnaiderman --- drivers/common/mlx5/meson.build | 9 +- drivers/common/mlx5/windows/mlx5_win_defs.h | 100 +++++++++++--------- drivers/net/mlx5/windows/mlx5_os.c | 4 +- 3 files changed, 65 insertions(+), 48 deletions(-) diff --git a/drivers/common/mlx5/meson.build b/drivers/common/mlx5/meson.build index 60ccd95cbc..9dc809f192 100644 --- a/drivers/common/mlx5/meson.build +++ b/drivers/common/mlx5/meson.build @@ -1,9 +1,14 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright 2019 Mellanox Technologies, Ltd -if not (is_linux or (is_windows and is_ms_linker)) +if not (is_linux or is_windows) build = false - reason = 'only supported on Linux and Windows build with clang' + reason = 'only supported on Linux and Windows' + subdir_done() +endif +if is_windows and not is_ms_linker and not meson.is_cross_build() + build = false + reason = 'MinGW is supported only for cross-compilation test' subdir_done() endif diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h index 3554e4a7ff..65da820c5e 100644 --- a/drivers/common/mlx5/windows/mlx5_win_defs.h +++ b/drivers/common/mlx5/windows/mlx5_win_defs.h @@ -2,8 +2,10 @@ * Copyright (C) Mellanox Technologies, Ltd. 2001-2020. */ -#ifndef __MLX5_WIN_DEFS_H__ -#define __MLX5_WIN_DEFS_H__ +#ifndef MLX5_WIN_DEFS_H +#define MLX5_WIN_DEFS_H + +#include enum { MLX5_CQE_OWNER_MASK = 1, @@ -40,29 +42,29 @@ enum { }; enum mlx5dv_cq_init_attr_mask { - MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE = 1 << 0, - MLX5DV_CQ_INIT_ATTR_MASK_FLAGS = 1 << 1, - MLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE = 1 << 2, + MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE = RTE_BIT32(0), + MLX5DV_CQ_INIT_ATTR_MASK_FLAG = RTE_BIT32(1), + MLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE = RTE_BIT32(2), }; enum mlx5dv_cqe_comp_res_format { - MLX5DV_CQE_RES_FORMAT_HASH = 1 << 0, - MLX5DV_CQE_RES_FORMAT_CSUM = 1 << 1, - MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, + MLX5DV_CQE_RES_FORMAT_HASH = RTE_BIT32(0), + MLX5DV_CQE_RES_FORMAT_CSUM = RTE_BIT32(1), + MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX = RTE_BIT32(2), }; enum ibv_access_flags { - IBV_ACCESS_LOCAL_WRITE = 1, - IBV_ACCESS_REMOTE_WRITE = 1 << 1, - IBV_ACCESS_REMOTE_READ = 1 << 2, - IBV_ACCESS_REMOTE_ATOMIC = 1 << 3, - IBV_ACCESS_MW_BIND = 1 << 4, - IBV_ACCESS_ZERO_BASED = 1 << 5, - IBV_ACCESS_ON_DEMAND = 1 << 6, + IBV_ACCESS_LOCAL_WRITE = RTE_BIT32(0), + IBV_ACCESS_REMOTE_WRITE = RTE_BIT32(1), + IBV_ACCESS_REMOTE_READ = RTE_BIT32(2), + IBV_ACCESS_REMOTE_ATOMIC = RTE_BIT32(3), + IBV_ACCESS_MW_BIND = RTE_BIT32(4), + IBV_ACCESS_ZERO_BASED = RTE_BIT32(5), + IBV_ACCESS_ON_DEMAND = RTE_BIT32(6), }; enum mlx5_ib_uapi_devx_create_event_channel_flags { - MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = 1 << 0, + MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = RTE_BIT32(0), }; #define MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA \ @@ -85,15 +87,15 @@ enum { }; enum { - MLX5_ETH_WQE_L3_CSUM = (1 << 6), - MLX5_ETH_WQE_L4_CSUM = (1 << 7), + MLX5_ETH_WQE_L3_CSUM = RTE_BIT32(6), + MLX5_ETH_WQE_L4_CSUM = RTE_BIT32(7), }; enum { - MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, - MLX5_WQE_CTRL_SOLICITED = 1 << 1, - MLX5_WQE_CTRL_FENCE = 4 << 5, - MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = 1 << 5, + MLX5_WQE_CTRL_SOLICITED = RTE_BIT32(1), + MLX5_WQE_CTRL_CQ_UPDATE = RTE_BIT32(3), + MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = RTE_BIT32(5), + MLX5_WQE_CTRL_FENCE = RTE_BIT32(7), }; enum { @@ -101,6 +103,11 @@ enum { MLX5_SEND_WQE_SHIFT = 6, }; +/* Verbs headers do not support -pedantic. */ +#ifdef PEDANTIC +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + /* * RX Hash fields enable to set which incoming packet's field should * participates in RX Hash. Each flag represent certain packet's field, @@ -110,18 +117,22 @@ enum { * TCP and UDP flags can't be enabled together on the same QP. */ enum ibv_rx_hash_fields { - IBV_RX_HASH_SRC_IPV4 = 1 << 0, - IBV_RX_HASH_DST_IPV4 = 1 << 1, - IBV_RX_HASH_SRC_IPV6 = 1 << 2, - IBV_RX_HASH_DST_IPV6 = 1 << 3, - IBV_RX_HASH_SRC_PORT_TCP = 1 << 4, - IBV_RX_HASH_DST_PORT_TCP = 1 << 5, - IBV_RX_HASH_SRC_PORT_UDP = 1 << 6, - IBV_RX_HASH_DST_PORT_UDP = 1 << 7, - IBV_RX_HASH_IPSEC_SPI = 1 << 8, - IBV_RX_HASH_INNER = (1 << 31), + IBV_RX_HASH_SRC_IPV4 = RTE_BIT32(0), + IBV_RX_HASH_DST_IPV4 = RTE_BIT32(1), + IBV_RX_HASH_SRC_IPV6 = RTE_BIT32(2), + IBV_RX_HASH_DST_IPV6 = RTE_BIT32(3), + IBV_RX_HASH_SRC_PORT_TCP = RTE_BIT32(4), + IBV_RX_HASH_DST_PORT_TCP = RTE_BIT32(5), + IBV_RX_HASH_SRC_PORT_UDP = RTE_BIT32(6), + IBV_RX_HASH_DST_PORT_UDP = RTE_BIT32(7), + IBV_RX_HASH_IPSEC_SPI = RTE_BIT32(8), + IBV_RX_HASH_INNER = RTE_BIT32(31), }; +#ifdef PEDANTIC +#pragma GCC diagnostic error "-Wpedantic" +#endif + enum { MLX5_RCV_DBR = 0, MLX5_SND_DBR = 1, @@ -141,9 +152,9 @@ enum { #endif enum ibv_flow_flags { - IBV_FLOW_ATTR_FLAGS_ALLOW_LOOP_BACK = 1 << 0, - IBV_FLOW_ATTR_FLAGS_DONT_TRAP = 1 << 1, - IBV_FLOW_ATTR_FLAGS_EGRESS = 1 << 2, + IBV_FLOW_ATTR_FLAGS_ALLOW_LOOP_BACK = RTE_BIT32(0), + IBV_FLOW_ATTR_FLAGS_DONT_TRAP = RTE_BIT32(1), + IBV_FLOW_ATTR_FLAGS_EGRESS = RTE_BIT32(2), }; enum ibv_flow_attr_type { @@ -240,11 +251,11 @@ struct mlx5_wqe_data_seg { rte_be64_t addr; }; -#define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) -#define IBV_DEVICE_RAW_IP_CSUM (1 << 26) -#define IBV_RAW_PACKET_CAP_CVLAN_STRIPPING (1 << 0) -#define IBV_RAW_PACKET_CAP_SCATTER_FCS (1 << 1) -#define IBV_QPT_RAW_PACKET 8 +#define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP RTE_BIT32(4) +#define IBV_DEVICE_RAW_IP_CSUM RTE_BIT32(26) +#define IBV_RAW_PACKET_CAP_CVLAN_STRIPPING RTE_BIT32(0) +#define IBV_RAW_PACKET_CAP_SCATTER_FCS RTE_BIT32(1) +#define IBV_QPT_RAW_PACKET 8 enum { MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, @@ -254,8 +265,9 @@ enum { }; enum { - MLX5_MATCH_OUTER_HEADERS = 1 << 0, - MLX5_MATCH_MISC_PARAMETERS = 1 << 1, - MLX5_MATCH_INNER_HEADERS = 1 << 2, + MLX5_MATCH_OUTER_HEADERS = RTE_BIT32(0), + MLX5_MATCH_MISC_PARAMETERS = RTE_BIT32(1), + MLX5_MATCH_INNER_HEADERS = RTE_BIT32(2), }; -#endif /* __MLX5_WIN_DEFS_H__ */ + +#endif /* MLX5_WIN_DEFS_H */ diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 77f04cc931..f401264b61 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -193,8 +193,8 @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh) * Once DPDK supports it, take max size from device attr. */ sh->dev_cap.ind_table_max_size = - RTE_MIN(1 << hca_attr->rss_ind_tbl_cap, - (unsigned int)RTE_ETH_RSS_RETA_SIZE_512); + RTE_MIN((uint32_t)1 << hca_attr->rss_ind_tbl_cap, + (uint32_t)RTE_ETH_RSS_RETA_SIZE_512); DRV_LOG(DEBUG, "Maximum Rx indirection table size is %u", sh->dev_cap.ind_table_max_size); } -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-04-09 21:45:41.022546000 +0800 +++ 0088-net-mlx5-fix-Windows-build-with-MinGW-GCC-12.patch 2023-04-09 21:45:38.709042200 +0800 @@ -1 +1 @@ -From 8ce24f0c8398b1129b64af83d49bf6fa8567c472 Mon Sep 17 00:00:00 2001 +From f081724c6bf5431062257f4893e078876eb904c8 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 8ce24f0c8398b1129b64af83d49bf6fa8567c472 ] @@ -12,2 +14,0 @@ - -Cc: stable@dpdk.org