* [PATCH 1/7] common/idpf: fix 64b timestamp roll over issue
[not found] <20230420091935.43116-1-wenjing.qiao@intel.com>
@ 2023-04-20 9:19 ` Wenjing Qiao
[not found] ` <20230421071603.55680-1-wenjing.qiao@intel.com>
2023-04-20 9:19 ` [PATCH 2/7] net/idpf: save master time by alarm Wenjing Qiao
` (4 subsequent siblings)
5 siblings, 1 reply; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-20 9:19 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
Reading MTS register at first packet will cause timestamp
roll over issue. To support caculating 64b timestamp, need
an alarm to save master time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/common/idpf/idpf_common_rxtx.c | 108 ++++++++++++-------------
drivers/common/idpf/idpf_common_rxtx.h | 3 +-
drivers/common/idpf/version.map | 1 +
3 files changed, 55 insertions(+), 57 deletions(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index fc87e3e243..19bcb94077 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -4,6 +4,7 @@
#include <rte_mbuf_dyn.h>
#include <rte_errno.h>
+#include <rte_alarm.h>
#include "idpf_common_rxtx.h"
@@ -442,56 +443,23 @@ idpf_qc_split_rxq_mbufs_alloc(struct idpf_rx_queue *rxq)
return 0;
}
-#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000
/* Helper function to convert a 32b nanoseconds timestamp to 64b. */
static inline uint64_t
-idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag,
- uint32_t in_timestamp)
+idpf_tstamp_convert_32b_64b(uint64_t time_hw, uint32_t in_timestamp)
{
-#ifdef RTE_ARCH_X86_64
- struct idpf_hw *hw = &ad->hw;
const uint64_t mask = 0xFFFFFFFF;
- uint32_t hi, lo, lo2, delta;
+ const uint32_t half_overflow_duration = 0x1 << 31;
+ uint32_t delta;
uint64_t ns;
- if (flag != 0) {
- IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
- IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |
- PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
- lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
- /*
- * On typical system, the delta between lo and lo2 is ~1000ns,
- * so 10000 seems a large-enough but not overly-big guard band.
- */
- if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
- lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- else
- lo2 = lo;
-
- if (lo2 < lo) {
- lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
- }
-
- ad->time_hw = ((uint64_t)hi << 32) | lo;
- }
-
- delta = (in_timestamp - (uint32_t)(ad->time_hw & mask));
- if (delta > (mask / 2)) {
- delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);
- ns = ad->time_hw - delta;
+ delta = (in_timestamp - (uint32_t)(time_hw & mask));
+ if (delta > half_overflow_duration) {
+ delta = ((uint32_t)(time_hw & mask) - in_timestamp);
+ ns = time_hw - delta;
} else {
- ns = ad->time_hw + delta;
+ ns = time_hw + delta;
}
-
return ns;
-#else /* !RTE_ARCH_X86_64 */
- RTE_SET_USED(ad);
- RTE_SET_USED(flag);
- RTE_SET_USED(in_timestamp);
- return 0;
-#endif /* RTE_ARCH_X86_64 */
}
#define IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S \
@@ -659,9 +627,6 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
rx_desc_ring = rxq->rx_ring;
ptype_tbl = rxq->adapter->ptype_tbl;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)
- rxq->hw_register_set = 1;
-
while (nb_rx < nb_pkts) {
rx_desc = &rx_desc_ring[rx_id];
@@ -720,10 +685,8 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rx_desc->ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1077,9 +1040,6 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
rx_ring = rxq->rx_ring;
ptype_tbl = rxq->adapter->ptype_tbl;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)
- rxq->hw_register_set = 1;
-
while (nb_rx < nb_pkts) {
rxdp = &rx_ring[rx_id];
rx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0);
@@ -1142,10 +1102,8 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1272,10 +1230,8 @@ idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1621,3 +1577,43 @@ idpf_qc_splitq_rx_vec_setup(struct idpf_rx_queue *rxq)
rxq->bufq2->ops = &def_rx_ops_vec;
return idpf_rxq_vec_setup_default(rxq->bufq2);
}
+
+#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000
+void
+idpf_dev_read_time_hw(void *cb_arg)
+{
+#ifdef RTE_ARCH_X86_64
+ struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg;
+ uint32_t hi, lo, lo2;
+ int rc = 0;
+ struct idpf_hw *hw = &ad->hw;
+
+ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
+ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
+ PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
+ lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
+ /*
+ * On typical system, the delta between lo and lo2 is ~1000ns,
+ * so 10000 seems a large-enough but not overly-big guard band.
+ */
+ if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
+ lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ else
+ lo2 = lo;
+
+ if (lo2 < lo) {
+ lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
+ }
+
+ ad->time_hw = ((uint64_t)hi << 32) | lo;
+#else /* !RTE_ARCH_X86_64 */
+ ad->time_hw = 0;
+#endif /* RTE_ARCH_X86_64 */
+
+ /* re-alarm watchdog */
+ rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg);
+ if (rc)
+ DRV_LOG(ERR, "Failed to reset device watchdog alarm");
+}
diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h
index 11260d07f9..af1425eb3f 100644
--- a/drivers/common/idpf/idpf_common_rxtx.h
+++ b/drivers/common/idpf/idpf_common_rxtx.h
@@ -142,7 +142,6 @@ struct idpf_rx_queue {
struct idpf_rx_queue *bufq2;
uint64_t offloads;
- uint32_t hw_register_set;
};
struct idpf_tx_entry {
@@ -300,4 +299,6 @@ __rte_internal
uint16_t idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
+__rte_internal
+void idpf_dev_read_time_hw(void *cb_arg);
#endif /* _IDPF_COMMON_RXTX_H_ */
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index 70334a1b03..c67c554911 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -14,6 +14,7 @@ INTERNAL {
idpf_dp_splitq_recv_pkts_avx512;
idpf_dp_splitq_xmit_pkts;
idpf_dp_splitq_xmit_pkts_avx512;
+ idpf_dev_read_time_hw;
idpf_qc_rx_thresh_check;
idpf_qc_rx_queue_release;
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 2/7] net/idpf: save master time by alarm
[not found] <20230420091935.43116-1-wenjing.qiao@intel.com>
2023-04-20 9:19 ` [PATCH 1/7] common/idpf: fix 64b timestamp roll over issue Wenjing Qiao
@ 2023-04-20 9:19 ` Wenjing Qiao
2023-04-20 9:19 ` [PATCH 3/7] net/cpfl: " Wenjing Qiao
` (3 subsequent siblings)
5 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-20 9:19 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
Using alarm to save master time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/net/idpf/idpf_ethdev.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index e02ec2ec5a..3f33ffbc78 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -761,6 +761,12 @@ idpf_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_set(1000 * 1000,
+ &idpf_dev_read_time_hw,
+ (void *)base);
+ }
+
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
@@ -810,6 +816,7 @@ static int
idpf_dev_stop(struct rte_eth_dev *dev)
{
struct idpf_vport *vport = dev->data->dev_private;
+ struct idpf_adapter *base = vport->adapter;
if (vport->stopped == 1)
return 0;
@@ -822,6 +829,11 @@ idpf_dev_stop(struct rte_eth_dev *dev)
idpf_vc_vectors_dealloc(vport);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_cancel(idpf_dev_read_time_hw,
+ base);
+ }
+
vport->stopped = 1;
return 0;
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 3/7] net/cpfl: save master time by alarm
[not found] <20230420091935.43116-1-wenjing.qiao@intel.com>
2023-04-20 9:19 ` [PATCH 1/7] common/idpf: fix 64b timestamp roll over issue Wenjing Qiao
2023-04-20 9:19 ` [PATCH 2/7] net/idpf: save master time by alarm Wenjing Qiao
@ 2023-04-20 9:19 ` Wenjing Qiao
2023-04-20 9:19 ` [PATCH 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
` (2 subsequent siblings)
5 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-20 9:19 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
Using alarm to save master time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/net/cpfl/cpfl_ethdev.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index ede730fd50..82d8147494 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -767,6 +767,12 @@ cpfl_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_set(1000 * 1000,
+ &idpf_dev_read_time_hw,
+ (void *)base);
+ }
+
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
@@ -816,6 +822,7 @@ static int
cpfl_dev_stop(struct rte_eth_dev *dev)
{
struct idpf_vport *vport = dev->data->dev_private;
+ struct idpf_adapter *base = vport->adapter;
if (vport->stopped == 1)
return 0;
@@ -828,6 +835,11 @@ cpfl_dev_stop(struct rte_eth_dev *dev)
idpf_vc_vectors_dealloc(vport);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_cancel(idpf_dev_read_time_hw,
+ base);
+ }
+
vport->stopped = 1;
return 0;
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 5/7] common/idpf: add timestamp enable flag for rxq
[not found] <20230420091935.43116-1-wenjing.qiao@intel.com>
` (2 preceding siblings ...)
2023-04-20 9:19 ` [PATCH 3/7] net/cpfl: " Wenjing Qiao
@ 2023-04-20 9:19 ` Wenjing Qiao
2023-04-20 9:19 ` [PATCH 6/7] net/cpfl: register timestamp mbuf when starting dev Wenjing Qiao
2023-04-20 9:19 ` [PATCH 7/7] net/idpf: " Wenjing Qiao
5 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-20 9:19 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
A rxq can be configured with timestamp offload.
So, add timestamp enable flag for rxq.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/common/idpf/idpf_common_rxtx.c | 3 ++-
drivers/common/idpf/idpf_common_rxtx.h | 2 ++
drivers/common/idpf/version.map | 3 +++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index 9c58f3fb11..7afe7afe3f 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -354,7 +354,7 @@ int
idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
{
int err;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
+ if (!rxq->ts_enable && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {
/* Register mbuf field and flag for Rx timestamp */
err = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
&idpf_timestamp_dynflag);
@@ -363,6 +363,7 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
"Cannot register mbuf field/flag for timestamp");
return -EINVAL;
}
+ rxq->ts_enable = TRUE;
}
return 0;
}
diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h
index af1425eb3f..cb7f5a3ba8 100644
--- a/drivers/common/idpf/idpf_common_rxtx.h
+++ b/drivers/common/idpf/idpf_common_rxtx.h
@@ -142,6 +142,8 @@ struct idpf_rx_queue {
struct idpf_rx_queue *bufq2;
uint64_t offloads;
+
+ bool ts_enable; /* if timestamp is enabled */
};
struct idpf_tx_entry {
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index c67c554911..15b42b4d2e 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -69,5 +69,8 @@ INTERNAL {
idpf_vport_rss_config;
idpf_vport_stats_update;
+ idpf_timestamp_dynfield_offset;
+ idpf_timestamp_dynflag;
+
local: *;
};
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 6/7] net/cpfl: register timestamp mbuf when starting dev
[not found] <20230420091935.43116-1-wenjing.qiao@intel.com>
` (3 preceding siblings ...)
2023-04-20 9:19 ` [PATCH 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
@ 2023-04-20 9:19 ` Wenjing Qiao
2023-04-20 9:19 ` [PATCH 7/7] net/idpf: " Wenjing Qiao
5 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-20 9:19 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
Due to only support timestamp at port level, registering
timestamp mbuf should be at dev start stage.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/cpfl/cpfl_ethdev.c | 7 +++++++
drivers/net/cpfl/cpfl_ethdev.h | 3 +++
drivers/net/cpfl/cpfl_rxtx.c | 2 ++
3 files changed, 12 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 82d8147494..416273f567 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -771,6 +771,13 @@ cpfl_dev_start(struct rte_eth_dev *dev)
rte_eal_alarm_set(1000 * 1000,
&idpf_dev_read_time_hw,
(void *)base);
+ /* Register mbuf field and flag for Rx timestamp */
+ ret = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
+ &idpf_timestamp_dynflag);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp");
+ return -EINVAL;
+ }
}
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h
index 200dfcac02..eec253bc77 100644
--- a/drivers/net/cpfl/cpfl_ethdev.h
+++ b/drivers/net/cpfl/cpfl_ethdev.h
@@ -57,6 +57,9 @@
/* Device IDs */
#define IDPF_DEV_ID_CPF 0x1453
+extern int idpf_timestamp_dynfield_offset;
+extern uint64_t idpf_timestamp_dynflag;
+
struct cpfl_vport_param {
struct cpfl_adapter_ext *adapter;
uint16_t devarg_id; /* arg id from user */
diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c
index de59b31b3d..cdb5b37da0 100644
--- a/drivers/net/cpfl/cpfl_rxtx.c
+++ b/drivers/net/cpfl/cpfl_rxtx.c
@@ -529,6 +529,8 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)
frame_size > rxq->rx_buf_len)
dev->data->scattered_rx = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ rxq->ts_enable = TRUE;
err = idpf_qc_ts_mbuf_register(rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u",
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 7/7] net/idpf: register timestamp mbuf when starting dev
[not found] <20230420091935.43116-1-wenjing.qiao@intel.com>
` (4 preceding siblings ...)
2023-04-20 9:19 ` [PATCH 6/7] net/cpfl: register timestamp mbuf when starting dev Wenjing Qiao
@ 2023-04-20 9:19 ` Wenjing Qiao
5 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-20 9:19 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
Due to only support timestamp at port level, registering
timestamp mbuf should be at dev start stage.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/idpf/idpf_ethdev.c | 7 +++++++
drivers/net/idpf/idpf_ethdev.h | 3 +++
drivers/net/idpf/idpf_rxtx.c | 3 +++
3 files changed, 13 insertions(+)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index 3f33ffbc78..7c43f51c25 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -765,6 +765,13 @@ idpf_dev_start(struct rte_eth_dev *dev)
rte_eal_alarm_set(1000 * 1000,
&idpf_dev_read_time_hw,
(void *)base);
+ /* Register mbuf field and flag for Rx timestamp */
+ ret = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
+ &idpf_timestamp_dynflag);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp");
+ return -EINVAL;
+ }
}
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
diff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h
index 3c2c932438..256e348710 100644
--- a/drivers/net/idpf/idpf_ethdev.h
+++ b/drivers/net/idpf/idpf_ethdev.h
@@ -55,6 +55,9 @@
#define IDPF_ALARM_INTERVAL 50000 /* us */
+extern int idpf_timestamp_dynfield_offset;
+extern uint64_t idpf_timestamp_dynflag;
+
struct idpf_vport_param {
struct idpf_adapter_ext *adapter;
uint16_t devarg_id; /* arg id from user */
diff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c
index 414f9a37f6..1aaf0142d2 100644
--- a/drivers/net/idpf/idpf_rxtx.c
+++ b/drivers/net/idpf/idpf_rxtx.c
@@ -529,6 +529,9 @@ idpf_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)
frame_size > rxq->rx_buf_len)
dev->data->scattered_rx = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ rxq->ts_enable = TRUE;
+
err = idpf_qc_ts_mbuf_register(rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "fail to residter timestamp mbuf %u",
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 1/7] common/idpf: fix 64b timestamp roll over issue
[not found] ` <20230421071603.55680-1-wenjing.qiao@intel.com>
@ 2023-04-21 7:15 ` Wenjing Qiao
[not found] ` <20230424091707.488045-1-wenjing.qiao@intel.com>
2023-04-21 7:15 ` [PATCH v2 2/7] net/idpf: save main time by alarm Wenjing Qiao
` (4 subsequent siblings)
5 siblings, 1 reply; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-21 7:15 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
Reading MTS register at first packet will cause timestamp
roll over issue. To support caculating 64b timestamp, need
an alarm to save master time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/common/idpf/idpf_common_rxtx.c | 108 ++++++++++++-------------
drivers/common/idpf/idpf_common_rxtx.h | 3 +-
drivers/common/idpf/version.map | 1 +
3 files changed, 55 insertions(+), 57 deletions(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index fc87e3e243..19bcb94077 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -4,6 +4,7 @@
#include <rte_mbuf_dyn.h>
#include <rte_errno.h>
+#include <rte_alarm.h>
#include "idpf_common_rxtx.h"
@@ -442,56 +443,23 @@ idpf_qc_split_rxq_mbufs_alloc(struct idpf_rx_queue *rxq)
return 0;
}
-#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000
/* Helper function to convert a 32b nanoseconds timestamp to 64b. */
static inline uint64_t
-idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag,
- uint32_t in_timestamp)
+idpf_tstamp_convert_32b_64b(uint64_t time_hw, uint32_t in_timestamp)
{
-#ifdef RTE_ARCH_X86_64
- struct idpf_hw *hw = &ad->hw;
const uint64_t mask = 0xFFFFFFFF;
- uint32_t hi, lo, lo2, delta;
+ const uint32_t half_overflow_duration = 0x1 << 31;
+ uint32_t delta;
uint64_t ns;
- if (flag != 0) {
- IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
- IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |
- PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
- lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
- /*
- * On typical system, the delta between lo and lo2 is ~1000ns,
- * so 10000 seems a large-enough but not overly-big guard band.
- */
- if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
- lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- else
- lo2 = lo;
-
- if (lo2 < lo) {
- lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
- }
-
- ad->time_hw = ((uint64_t)hi << 32) | lo;
- }
-
- delta = (in_timestamp - (uint32_t)(ad->time_hw & mask));
- if (delta > (mask / 2)) {
- delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);
- ns = ad->time_hw - delta;
+ delta = (in_timestamp - (uint32_t)(time_hw & mask));
+ if (delta > half_overflow_duration) {
+ delta = ((uint32_t)(time_hw & mask) - in_timestamp);
+ ns = time_hw - delta;
} else {
- ns = ad->time_hw + delta;
+ ns = time_hw + delta;
}
-
return ns;
-#else /* !RTE_ARCH_X86_64 */
- RTE_SET_USED(ad);
- RTE_SET_USED(flag);
- RTE_SET_USED(in_timestamp);
- return 0;
-#endif /* RTE_ARCH_X86_64 */
}
#define IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S \
@@ -659,9 +627,6 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
rx_desc_ring = rxq->rx_ring;
ptype_tbl = rxq->adapter->ptype_tbl;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)
- rxq->hw_register_set = 1;
-
while (nb_rx < nb_pkts) {
rx_desc = &rx_desc_ring[rx_id];
@@ -720,10 +685,8 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rx_desc->ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1077,9 +1040,6 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
rx_ring = rxq->rx_ring;
ptype_tbl = rxq->adapter->ptype_tbl;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)
- rxq->hw_register_set = 1;
-
while (nb_rx < nb_pkts) {
rxdp = &rx_ring[rx_id];
rx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0);
@@ -1142,10 +1102,8 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1272,10 +1230,8 @@ idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1621,3 +1577,43 @@ idpf_qc_splitq_rx_vec_setup(struct idpf_rx_queue *rxq)
rxq->bufq2->ops = &def_rx_ops_vec;
return idpf_rxq_vec_setup_default(rxq->bufq2);
}
+
+#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000
+void
+idpf_dev_read_time_hw(void *cb_arg)
+{
+#ifdef RTE_ARCH_X86_64
+ struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg;
+ uint32_t hi, lo, lo2;
+ int rc = 0;
+ struct idpf_hw *hw = &ad->hw;
+
+ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
+ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
+ PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
+ lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
+ /*
+ * On typical system, the delta between lo and lo2 is ~1000ns,
+ * so 10000 seems a large-enough but not overly-big guard band.
+ */
+ if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
+ lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ else
+ lo2 = lo;
+
+ if (lo2 < lo) {
+ lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
+ }
+
+ ad->time_hw = ((uint64_t)hi << 32) | lo;
+#else /* !RTE_ARCH_X86_64 */
+ ad->time_hw = 0;
+#endif /* RTE_ARCH_X86_64 */
+
+ /* re-alarm watchdog */
+ rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg);
+ if (rc)
+ DRV_LOG(ERR, "Failed to reset device watchdog alarm");
+}
diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h
index 11260d07f9..af1425eb3f 100644
--- a/drivers/common/idpf/idpf_common_rxtx.h
+++ b/drivers/common/idpf/idpf_common_rxtx.h
@@ -142,7 +142,6 @@ struct idpf_rx_queue {
struct idpf_rx_queue *bufq2;
uint64_t offloads;
- uint32_t hw_register_set;
};
struct idpf_tx_entry {
@@ -300,4 +299,6 @@ __rte_internal
uint16_t idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
+__rte_internal
+void idpf_dev_read_time_hw(void *cb_arg);
#endif /* _IDPF_COMMON_RXTX_H_ */
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index 70334a1b03..c67c554911 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -14,6 +14,7 @@ INTERNAL {
idpf_dp_splitq_recv_pkts_avx512;
idpf_dp_splitq_xmit_pkts;
idpf_dp_splitq_xmit_pkts_avx512;
+ idpf_dev_read_time_hw;
idpf_qc_rx_thresh_check;
idpf_qc_rx_queue_release;
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 2/7] net/idpf: save main time by alarm
[not found] ` <20230421071603.55680-1-wenjing.qiao@intel.com>
2023-04-21 7:15 ` [PATCH v2 " Wenjing Qiao
@ 2023-04-21 7:15 ` Wenjing Qiao
2023-04-28 2:46 ` Zhang, Qi Z
2023-04-21 7:15 ` [PATCH v2 3/7] net/cpfl: " Wenjing Qiao
` (3 subsequent siblings)
5 siblings, 1 reply; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-21 7:15 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
Using alarm to save main time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/net/idpf/idpf_ethdev.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index e02ec2ec5a..3f33ffbc78 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -761,6 +761,12 @@ idpf_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_set(1000 * 1000,
+ &idpf_dev_read_time_hw,
+ (void *)base);
+ }
+
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
@@ -810,6 +816,7 @@ static int
idpf_dev_stop(struct rte_eth_dev *dev)
{
struct idpf_vport *vport = dev->data->dev_private;
+ struct idpf_adapter *base = vport->adapter;
if (vport->stopped == 1)
return 0;
@@ -822,6 +829,11 @@ idpf_dev_stop(struct rte_eth_dev *dev)
idpf_vc_vectors_dealloc(vport);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_cancel(idpf_dev_read_time_hw,
+ base);
+ }
+
vport->stopped = 1;
return 0;
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 3/7] net/cpfl: save main time by alarm
[not found] ` <20230421071603.55680-1-wenjing.qiao@intel.com>
2023-04-21 7:15 ` [PATCH v2 " Wenjing Qiao
2023-04-21 7:15 ` [PATCH v2 2/7] net/idpf: save main time by alarm Wenjing Qiao
@ 2023-04-21 7:15 ` Wenjing Qiao
2023-04-21 7:16 ` [PATCH v2 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
` (2 subsequent siblings)
5 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-21 7:15 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
Using alarm to save main time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/net/cpfl/cpfl_ethdev.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index ede730fd50..82d8147494 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -767,6 +767,12 @@ cpfl_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_set(1000 * 1000,
+ &idpf_dev_read_time_hw,
+ (void *)base);
+ }
+
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
@@ -816,6 +822,7 @@ static int
cpfl_dev_stop(struct rte_eth_dev *dev)
{
struct idpf_vport *vport = dev->data->dev_private;
+ struct idpf_adapter *base = vport->adapter;
if (vport->stopped == 1)
return 0;
@@ -828,6 +835,11 @@ cpfl_dev_stop(struct rte_eth_dev *dev)
idpf_vc_vectors_dealloc(vport);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_cancel(idpf_dev_read_time_hw,
+ base);
+ }
+
vport->stopped = 1;
return 0;
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 5/7] common/idpf: add timestamp enable flag for rxq
[not found] ` <20230421071603.55680-1-wenjing.qiao@intel.com>
` (2 preceding siblings ...)
2023-04-21 7:15 ` [PATCH v2 3/7] net/cpfl: " Wenjing Qiao
@ 2023-04-21 7:16 ` Wenjing Qiao
2023-04-21 7:16 ` [PATCH v2 6/7] net/cpfl: register timestamp mbuf when starting dev Wenjing Qiao
2023-04-21 7:16 ` [PATCH v2 7/7] net/idpf: " Wenjing Qiao
5 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-21 7:16 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
A rxq can be configured with timestamp offload.
So, add timestamp enable flag for rxq.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/common/idpf/idpf_common_rxtx.c | 3 ++-
drivers/common/idpf/idpf_common_rxtx.h | 2 ++
drivers/common/idpf/version.map | 3 +++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index 9c58f3fb11..7afe7afe3f 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -354,7 +354,7 @@ int
idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
{
int err;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
+ if (!rxq->ts_enable && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {
/* Register mbuf field and flag for Rx timestamp */
err = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
&idpf_timestamp_dynflag);
@@ -363,6 +363,7 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
"Cannot register mbuf field/flag for timestamp");
return -EINVAL;
}
+ rxq->ts_enable = TRUE;
}
return 0;
}
diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h
index af1425eb3f..cb7f5a3ba8 100644
--- a/drivers/common/idpf/idpf_common_rxtx.h
+++ b/drivers/common/idpf/idpf_common_rxtx.h
@@ -142,6 +142,8 @@ struct idpf_rx_queue {
struct idpf_rx_queue *bufq2;
uint64_t offloads;
+
+ bool ts_enable; /* if timestamp is enabled */
};
struct idpf_tx_entry {
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index c67c554911..15b42b4d2e 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -69,5 +69,8 @@ INTERNAL {
idpf_vport_rss_config;
idpf_vport_stats_update;
+ idpf_timestamp_dynfield_offset;
+ idpf_timestamp_dynflag;
+
local: *;
};
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 6/7] net/cpfl: register timestamp mbuf when starting dev
[not found] ` <20230421071603.55680-1-wenjing.qiao@intel.com>
` (3 preceding siblings ...)
2023-04-21 7:16 ` [PATCH v2 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
@ 2023-04-21 7:16 ` Wenjing Qiao
2023-04-21 7:16 ` [PATCH v2 7/7] net/idpf: " Wenjing Qiao
5 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-21 7:16 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
Due to only support timestamp at port level, registering
timestamp mbuf should be at dev start stage.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/cpfl/cpfl_ethdev.c | 7 +++++++
drivers/net/cpfl/cpfl_ethdev.h | 3 +++
drivers/net/cpfl/cpfl_rxtx.c | 2 ++
3 files changed, 12 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 82d8147494..416273f567 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -771,6 +771,13 @@ cpfl_dev_start(struct rte_eth_dev *dev)
rte_eal_alarm_set(1000 * 1000,
&idpf_dev_read_time_hw,
(void *)base);
+ /* Register mbuf field and flag for Rx timestamp */
+ ret = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
+ &idpf_timestamp_dynflag);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp");
+ return -EINVAL;
+ }
}
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h
index 200dfcac02..eec253bc77 100644
--- a/drivers/net/cpfl/cpfl_ethdev.h
+++ b/drivers/net/cpfl/cpfl_ethdev.h
@@ -57,6 +57,9 @@
/* Device IDs */
#define IDPF_DEV_ID_CPF 0x1453
+extern int idpf_timestamp_dynfield_offset;
+extern uint64_t idpf_timestamp_dynflag;
+
struct cpfl_vport_param {
struct cpfl_adapter_ext *adapter;
uint16_t devarg_id; /* arg id from user */
diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c
index de59b31b3d..cdb5b37da0 100644
--- a/drivers/net/cpfl/cpfl_rxtx.c
+++ b/drivers/net/cpfl/cpfl_rxtx.c
@@ -529,6 +529,8 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)
frame_size > rxq->rx_buf_len)
dev->data->scattered_rx = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ rxq->ts_enable = TRUE;
err = idpf_qc_ts_mbuf_register(rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u",
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v2 7/7] net/idpf: register timestamp mbuf when starting dev
[not found] ` <20230421071603.55680-1-wenjing.qiao@intel.com>
` (4 preceding siblings ...)
2023-04-21 7:16 ` [PATCH v2 6/7] net/cpfl: register timestamp mbuf when starting dev Wenjing Qiao
@ 2023-04-21 7:16 ` Wenjing Qiao
5 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-21 7:16 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang; +Cc: dev, Wenjing Qiao, stable
Due to only support timestamp at port level, registering
timestamp mbuf should be at dev start stage.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/idpf/idpf_ethdev.c | 7 +++++++
drivers/net/idpf/idpf_ethdev.h | 3 +++
drivers/net/idpf/idpf_rxtx.c | 3 +++
3 files changed, 13 insertions(+)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index 3f33ffbc78..7c43f51c25 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -765,6 +765,13 @@ idpf_dev_start(struct rte_eth_dev *dev)
rte_eal_alarm_set(1000 * 1000,
&idpf_dev_read_time_hw,
(void *)base);
+ /* Register mbuf field and flag for Rx timestamp */
+ ret = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
+ &idpf_timestamp_dynflag);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp");
+ return -EINVAL;
+ }
}
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
diff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h
index 3c2c932438..256e348710 100644
--- a/drivers/net/idpf/idpf_ethdev.h
+++ b/drivers/net/idpf/idpf_ethdev.h
@@ -55,6 +55,9 @@
#define IDPF_ALARM_INTERVAL 50000 /* us */
+extern int idpf_timestamp_dynfield_offset;
+extern uint64_t idpf_timestamp_dynflag;
+
struct idpf_vport_param {
struct idpf_adapter_ext *adapter;
uint16_t devarg_id; /* arg id from user */
diff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c
index 414f9a37f6..1aaf0142d2 100644
--- a/drivers/net/idpf/idpf_rxtx.c
+++ b/drivers/net/idpf/idpf_rxtx.c
@@ -529,6 +529,9 @@ idpf_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)
frame_size > rxq->rx_buf_len)
dev->data->scattered_rx = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ rxq->ts_enable = TRUE;
+
err = idpf_qc_ts_mbuf_register(rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "fail to residter timestamp mbuf %u",
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v3 1/7] common/idpf: fix 64b timestamp roll over issue
[not found] ` <20230424091707.488045-1-wenjing.qiao@intel.com>
@ 2023-04-24 9:17 ` Wenjing Qiao
[not found] ` <20230519083110.809913-1-wenjing.qiao@intel.com>
2023-04-24 9:17 ` [PATCH v3 2/7] net/idpf: save main time by alarm Wenjing Qiao
` (5 subsequent siblings)
6 siblings, 1 reply; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-24 9:17 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
Reading MTS register at first packet will cause timestamp
roll over issue. To support calculating 64b timestamp, need
an alarm to save main time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/common/idpf/idpf_common_rxtx.c | 108 ++++++++++++-------------
drivers/common/idpf/idpf_common_rxtx.h | 3 +-
drivers/common/idpf/version.map | 1 +
3 files changed, 55 insertions(+), 57 deletions(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index fc87e3e243..19bcb94077 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -4,6 +4,7 @@
#include <rte_mbuf_dyn.h>
#include <rte_errno.h>
+#include <rte_alarm.h>
#include "idpf_common_rxtx.h"
@@ -442,56 +443,23 @@ idpf_qc_split_rxq_mbufs_alloc(struct idpf_rx_queue *rxq)
return 0;
}
-#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000
/* Helper function to convert a 32b nanoseconds timestamp to 64b. */
static inline uint64_t
-idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag,
- uint32_t in_timestamp)
+idpf_tstamp_convert_32b_64b(uint64_t time_hw, uint32_t in_timestamp)
{
-#ifdef RTE_ARCH_X86_64
- struct idpf_hw *hw = &ad->hw;
const uint64_t mask = 0xFFFFFFFF;
- uint32_t hi, lo, lo2, delta;
+ const uint32_t half_overflow_duration = 0x1 << 31;
+ uint32_t delta;
uint64_t ns;
- if (flag != 0) {
- IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
- IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |
- PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
- lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
- /*
- * On typical system, the delta between lo and lo2 is ~1000ns,
- * so 10000 seems a large-enough but not overly-big guard band.
- */
- if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
- lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- else
- lo2 = lo;
-
- if (lo2 < lo) {
- lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
- }
-
- ad->time_hw = ((uint64_t)hi << 32) | lo;
- }
-
- delta = (in_timestamp - (uint32_t)(ad->time_hw & mask));
- if (delta > (mask / 2)) {
- delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);
- ns = ad->time_hw - delta;
+ delta = (in_timestamp - (uint32_t)(time_hw & mask));
+ if (delta > half_overflow_duration) {
+ delta = ((uint32_t)(time_hw & mask) - in_timestamp);
+ ns = time_hw - delta;
} else {
- ns = ad->time_hw + delta;
+ ns = time_hw + delta;
}
-
return ns;
-#else /* !RTE_ARCH_X86_64 */
- RTE_SET_USED(ad);
- RTE_SET_USED(flag);
- RTE_SET_USED(in_timestamp);
- return 0;
-#endif /* RTE_ARCH_X86_64 */
}
#define IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S \
@@ -659,9 +627,6 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
rx_desc_ring = rxq->rx_ring;
ptype_tbl = rxq->adapter->ptype_tbl;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)
- rxq->hw_register_set = 1;
-
while (nb_rx < nb_pkts) {
rx_desc = &rx_desc_ring[rx_id];
@@ -720,10 +685,8 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rx_desc->ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1077,9 +1040,6 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
rx_ring = rxq->rx_ring;
ptype_tbl = rxq->adapter->ptype_tbl;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)
- rxq->hw_register_set = 1;
-
while (nb_rx < nb_pkts) {
rxdp = &rx_ring[rx_id];
rx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0);
@@ -1142,10 +1102,8 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1272,10 +1230,8 @@ idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1621,3 +1577,43 @@ idpf_qc_splitq_rx_vec_setup(struct idpf_rx_queue *rxq)
rxq->bufq2->ops = &def_rx_ops_vec;
return idpf_rxq_vec_setup_default(rxq->bufq2);
}
+
+#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000
+void
+idpf_dev_read_time_hw(void *cb_arg)
+{
+#ifdef RTE_ARCH_X86_64
+ struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg;
+ uint32_t hi, lo, lo2;
+ int rc = 0;
+ struct idpf_hw *hw = &ad->hw;
+
+ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
+ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
+ PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
+ lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
+ /*
+ * On typical system, the delta between lo and lo2 is ~1000ns,
+ * so 10000 seems a large-enough but not overly-big guard band.
+ */
+ if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
+ lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ else
+ lo2 = lo;
+
+ if (lo2 < lo) {
+ lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
+ }
+
+ ad->time_hw = ((uint64_t)hi << 32) | lo;
+#else /* !RTE_ARCH_X86_64 */
+ ad->time_hw = 0;
+#endif /* RTE_ARCH_X86_64 */
+
+ /* re-alarm watchdog */
+ rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg);
+ if (rc)
+ DRV_LOG(ERR, "Failed to reset device watchdog alarm");
+}
diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h
index 11260d07f9..af1425eb3f 100644
--- a/drivers/common/idpf/idpf_common_rxtx.h
+++ b/drivers/common/idpf/idpf_common_rxtx.h
@@ -142,7 +142,6 @@ struct idpf_rx_queue {
struct idpf_rx_queue *bufq2;
uint64_t offloads;
- uint32_t hw_register_set;
};
struct idpf_tx_entry {
@@ -300,4 +299,6 @@ __rte_internal
uint16_t idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
+__rte_internal
+void idpf_dev_read_time_hw(void *cb_arg);
#endif /* _IDPF_COMMON_RXTX_H_ */
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index 70334a1b03..c67c554911 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -14,6 +14,7 @@ INTERNAL {
idpf_dp_splitq_recv_pkts_avx512;
idpf_dp_splitq_xmit_pkts;
idpf_dp_splitq_xmit_pkts_avx512;
+ idpf_dev_read_time_hw;
idpf_qc_rx_thresh_check;
idpf_qc_rx_queue_release;
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v3 2/7] net/idpf: save main time by alarm
[not found] ` <20230424091707.488045-1-wenjing.qiao@intel.com>
2023-04-24 9:17 ` [PATCH v3 " Wenjing Qiao
@ 2023-04-24 9:17 ` Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 3/7] net/cpfl: " Wenjing Qiao
` (4 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-24 9:17 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
Using alarm to save main time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/net/idpf/idpf_ethdev.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index e02ec2ec5a..3f33ffbc78 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -761,6 +761,12 @@ idpf_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_set(1000 * 1000,
+ &idpf_dev_read_time_hw,
+ (void *)base);
+ }
+
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
@@ -810,6 +816,7 @@ static int
idpf_dev_stop(struct rte_eth_dev *dev)
{
struct idpf_vport *vport = dev->data->dev_private;
+ struct idpf_adapter *base = vport->adapter;
if (vport->stopped == 1)
return 0;
@@ -822,6 +829,11 @@ idpf_dev_stop(struct rte_eth_dev *dev)
idpf_vc_vectors_dealloc(vport);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_cancel(idpf_dev_read_time_hw,
+ base);
+ }
+
vport->stopped = 1;
return 0;
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v3 3/7] net/cpfl: save main time by alarm
[not found] ` <20230424091707.488045-1-wenjing.qiao@intel.com>
2023-04-24 9:17 ` [PATCH v3 " Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 2/7] net/idpf: save main time by alarm Wenjing Qiao
@ 2023-04-24 9:17 ` Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 4/7] common/idpf: enhance timestamp offload feature for ACC Wenjing Qiao
` (3 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-24 9:17 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
Using alarm to save main time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/net/cpfl/cpfl_ethdev.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index ede730fd50..82d8147494 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -767,6 +767,12 @@ cpfl_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_set(1000 * 1000,
+ &idpf_dev_read_time_hw,
+ (void *)base);
+ }
+
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
@@ -816,6 +822,7 @@ static int
cpfl_dev_stop(struct rte_eth_dev *dev)
{
struct idpf_vport *vport = dev->data->dev_private;
+ struct idpf_adapter *base = vport->adapter;
if (vport->stopped == 1)
return 0;
@@ -828,6 +835,11 @@ cpfl_dev_stop(struct rte_eth_dev *dev)
idpf_vc_vectors_dealloc(vport);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ rte_eal_alarm_cancel(idpf_dev_read_time_hw,
+ base);
+ }
+
vport->stopped = 1;
return 0;
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v3 4/7] common/idpf: enhance timestamp offload feature for ACC
[not found] ` <20230424091707.488045-1-wenjing.qiao@intel.com>
` (2 preceding siblings ...)
2023-04-24 9:17 ` [PATCH v3 3/7] net/cpfl: " Wenjing Qiao
@ 2023-04-24 9:17 ` Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
` (2 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-24 9:17 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
For ACC, getting main time from MTS registers by shared memory.
Notice: it is a workaround, and it will be removed after generic
solution are provided.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
config/meson.build | 3 ++
drivers/common/idpf/base/idpf_osdep.h | 48 ++++++++++++++++++++++++++
drivers/common/idpf/idpf_common_rxtx.c | 30 +++++++++++++---
meson_options.txt | 2 ++
4 files changed, 79 insertions(+), 4 deletions(-)
diff --git a/config/meson.build b/config/meson.build
index fa730a1b14..8d74f301b4 100644
--- a/config/meson.build
+++ b/config/meson.build
@@ -316,6 +316,9 @@ endif
if get_option('mbuf_refcnt_atomic')
dpdk_conf.set('RTE_MBUF_REFCNT_ATOMIC', true)
endif
+if get_option('enable_acc_timestamp')
+ dpdk_conf.set('IDPF_ACC_TIMESTAMP', true)
+endif
dpdk_conf.set10('RTE_IOVA_IN_MBUF', get_option('enable_iova_as_pa'))
compile_time_cpuflags = []
diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h
index 99ae9cf60a..e634939a51 100644
--- a/drivers/common/idpf/base/idpf_osdep.h
+++ b/drivers/common/idpf/base/idpf_osdep.h
@@ -24,6 +24,13 @@
#include <rte_random.h>
#include <rte_io.h>
+#ifdef IDPF_ACC_TIMESTAMP
+#include <stdio.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <sys/mman.h>
+#endif /* IDPF_ACC_TIMESTAMP */
+
#define INLINE inline
#define STATIC static
@@ -361,4 +368,45 @@ idpf_hweight32(u32 num)
#endif
+#ifdef IDPF_ACC_TIMESTAMP
+#define IDPF_ACC_TIMESYNC_BASE_ADDR 0x480D500000
+#define IDPF_ACC_GLTSYN_TIME_H (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x1C)
+#define IDPF_ACC_GLTSYN_TIME_L (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x10)
+
+inline uint32_t
+idpf_mmap_r32(uint64_t pa)
+{
+ int fd;
+ void *bp, *vp;
+ uint32_t rval = 0xdeadbeef;
+ uint32_t ps, ml, of;
+
+ fd = open("/dev/mem", (O_RDWR | O_SYNC));
+ if (fd == -1) {
+ perror("/dev/mem");
+ return -1;
+ }
+ ml = ps = getpagesize();
+ of = (uint32_t)pa & (ps - 1);
+ if (of + (sizeof(uint32_t) * 4) > ps)
+ ml *= 2;
+ bp = mmap(NULL, ml, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, pa & ~(uint64_t)(ps - 1));
+ if (bp == MAP_FAILED) {
+ perror("mmap");
+ goto done;
+ }
+
+ vp = (char *)bp + of;
+
+ rval = *(volatile uint32_t *)vp;
+ if (munmap(bp, ml) == -1)
+ perror("munmap");
+done:
+ close(fd);
+
+ return rval;
+}
+
+#endif /* IDPF_ACC_TIMESTAMP */
+
#endif /* _IDPF_OSDEP_H_ */
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index 19bcb94077..9c58f3fb11 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -1582,12 +1582,36 @@ idpf_qc_splitq_rx_vec_setup(struct idpf_rx_queue *rxq)
void
idpf_dev_read_time_hw(void *cb_arg)
{
-#ifdef RTE_ARCH_X86_64
struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg;
uint32_t hi, lo, lo2;
int rc = 0;
+#ifndef IDPF_ACC_TIMESTAMP
struct idpf_hw *hw = &ad->hw;
+#endif /* !IDPF_ACC_TIMESTAMP */
+#ifdef IDPF_ACC_TIMESTAMP
+
+ lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);
+ hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H);
+ DRV_LOG(DEBUG, "lo : %X,", lo);
+ DRV_LOG(DEBUG, "hi : %X,", hi);
+ /*
+ * On typical system, the delta between lo and lo2 is ~1000ns,
+ * so 10000 seems a large-enough but not overly-big guard band.
+ */
+ if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
+ lo2 = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);
+ else
+ lo2 = lo;
+
+ if (lo2 < lo) {
+ lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);
+ hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H);
+ }
+
+ ad->time_hw = ((uint64_t)hi << 32) | lo;
+
+#else /* !IDPF_ACC_TIMESTAMP */
IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
@@ -1608,9 +1632,7 @@ idpf_dev_read_time_hw(void *cb_arg)
}
ad->time_hw = ((uint64_t)hi << 32) | lo;
-#else /* !RTE_ARCH_X86_64 */
- ad->time_hw = 0;
-#endif /* RTE_ARCH_X86_64 */
+#endif /* IDPF_ACC_TIMESTAMP */
/* re-alarm watchdog */
rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg);
diff --git a/meson_options.txt b/meson_options.txt
index 82c8297065..31fc634aa0 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -52,3 +52,5 @@ option('tests', type: 'boolean', value: true, description:
'build unit tests')
option('use_hpet', type: 'boolean', value: false, description:
'use HPET timer in EAL')
+option('enable_acc_timestamp', type: 'boolean', value: false, description:
+ 'enable timestamp on ACC.')
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v3 5/7] common/idpf: add timestamp enable flag for rxq
[not found] ` <20230424091707.488045-1-wenjing.qiao@intel.com>
` (3 preceding siblings ...)
2023-04-24 9:17 ` [PATCH v3 4/7] common/idpf: enhance timestamp offload feature for ACC Wenjing Qiao
@ 2023-04-24 9:17 ` Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 6/7] net/cpfl: register timestamp mbuf when starting dev Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 7/7] net/idpf: " Wenjing Qiao
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-24 9:17 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
A rxq can be configured with timestamp offload.
So, add timestamp enable flag for rxq.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/common/idpf/idpf_common_rxtx.c | 3 ++-
drivers/common/idpf/idpf_common_rxtx.h | 2 ++
drivers/common/idpf/version.map | 3 +++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index 9c58f3fb11..7afe7afe3f 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -354,7 +354,7 @@ int
idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
{
int err;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
+ if (!rxq->ts_enable && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {
/* Register mbuf field and flag for Rx timestamp */
err = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
&idpf_timestamp_dynflag);
@@ -363,6 +363,7 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
"Cannot register mbuf field/flag for timestamp");
return -EINVAL;
}
+ rxq->ts_enable = TRUE;
}
return 0;
}
diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h
index af1425eb3f..cb7f5a3ba8 100644
--- a/drivers/common/idpf/idpf_common_rxtx.h
+++ b/drivers/common/idpf/idpf_common_rxtx.h
@@ -142,6 +142,8 @@ struct idpf_rx_queue {
struct idpf_rx_queue *bufq2;
uint64_t offloads;
+
+ bool ts_enable; /* if timestamp is enabled */
};
struct idpf_tx_entry {
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index c67c554911..15b42b4d2e 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -69,5 +69,8 @@ INTERNAL {
idpf_vport_rss_config;
idpf_vport_stats_update;
+ idpf_timestamp_dynfield_offset;
+ idpf_timestamp_dynflag;
+
local: *;
};
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v3 6/7] net/cpfl: register timestamp mbuf when starting dev
[not found] ` <20230424091707.488045-1-wenjing.qiao@intel.com>
` (4 preceding siblings ...)
2023-04-24 9:17 ` [PATCH v3 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
@ 2023-04-24 9:17 ` Wenjing Qiao
2023-04-28 3:24 ` Zhang, Qi Z
2023-04-24 9:17 ` [PATCH v3 7/7] net/idpf: " Wenjing Qiao
6 siblings, 1 reply; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-24 9:17 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
Due to only support timestamp at port level, registering
timestamp mbuf should be at dev start stage.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/cpfl/cpfl_ethdev.c | 7 +++++++
drivers/net/cpfl/cpfl_ethdev.h | 3 +++
drivers/net/cpfl/cpfl_rxtx.c | 2 ++
3 files changed, 12 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 82d8147494..416273f567 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -771,6 +771,13 @@ cpfl_dev_start(struct rte_eth_dev *dev)
rte_eal_alarm_set(1000 * 1000,
&idpf_dev_read_time_hw,
(void *)base);
+ /* Register mbuf field and flag for Rx timestamp */
+ ret = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
+ &idpf_timestamp_dynflag);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp");
+ return -EINVAL;
+ }
}
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h
index 200dfcac02..eec253bc77 100644
--- a/drivers/net/cpfl/cpfl_ethdev.h
+++ b/drivers/net/cpfl/cpfl_ethdev.h
@@ -57,6 +57,9 @@
/* Device IDs */
#define IDPF_DEV_ID_CPF 0x1453
+extern int idpf_timestamp_dynfield_offset;
+extern uint64_t idpf_timestamp_dynflag;
+
struct cpfl_vport_param {
struct cpfl_adapter_ext *adapter;
uint16_t devarg_id; /* arg id from user */
diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c
index de59b31b3d..cdb5b37da0 100644
--- a/drivers/net/cpfl/cpfl_rxtx.c
+++ b/drivers/net/cpfl/cpfl_rxtx.c
@@ -529,6 +529,8 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)
frame_size > rxq->rx_buf_len)
dev->data->scattered_rx = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ rxq->ts_enable = TRUE;
err = idpf_qc_ts_mbuf_register(rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u",
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v3 7/7] net/idpf: register timestamp mbuf when starting dev
[not found] ` <20230424091707.488045-1-wenjing.qiao@intel.com>
` (5 preceding siblings ...)
2023-04-24 9:17 ` [PATCH v3 6/7] net/cpfl: register timestamp mbuf when starting dev Wenjing Qiao
@ 2023-04-24 9:17 ` Wenjing Qiao
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-04-24 9:17 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
Due to only support timestamp at port level, registering
timestamp mbuf should be at dev start stage.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/idpf/idpf_ethdev.c | 7 +++++++
drivers/net/idpf/idpf_ethdev.h | 3 +++
drivers/net/idpf/idpf_rxtx.c | 3 +++
3 files changed, 13 insertions(+)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index 3f33ffbc78..7c43f51c25 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -765,6 +765,13 @@ idpf_dev_start(struct rte_eth_dev *dev)
rte_eal_alarm_set(1000 * 1000,
&idpf_dev_read_time_hw,
(void *)base);
+ /* Register mbuf field and flag for Rx timestamp */
+ ret = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
+ &idpf_timestamp_dynflag);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp");
+ return -EINVAL;
+ }
}
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
diff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h
index 3c2c932438..256e348710 100644
--- a/drivers/net/idpf/idpf_ethdev.h
+++ b/drivers/net/idpf/idpf_ethdev.h
@@ -55,6 +55,9 @@
#define IDPF_ALARM_INTERVAL 50000 /* us */
+extern int idpf_timestamp_dynfield_offset;
+extern uint64_t idpf_timestamp_dynflag;
+
struct idpf_vport_param {
struct idpf_adapter_ext *adapter;
uint16_t devarg_id; /* arg id from user */
diff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c
index 414f9a37f6..1aaf0142d2 100644
--- a/drivers/net/idpf/idpf_rxtx.c
+++ b/drivers/net/idpf/idpf_rxtx.c
@@ -529,6 +529,9 @@ idpf_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)
frame_size > rxq->rx_buf_len)
dev->data->scattered_rx = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ rxq->ts_enable = TRUE;
+
err = idpf_qc_ts_mbuf_register(rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "fail to residter timestamp mbuf %u",
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* RE: [PATCH v2 2/7] net/idpf: save main time by alarm
2023-04-21 7:15 ` [PATCH v2 2/7] net/idpf: save main time by alarm Wenjing Qiao
@ 2023-04-28 2:46 ` Zhang, Qi Z
0 siblings, 0 replies; 29+ messages in thread
From: Zhang, Qi Z @ 2023-04-28 2:46 UTC (permalink / raw)
To: Qiao, Wenjing, Wu, Jingjing, Xing, Beilei; +Cc: dev, stable
> -----Original Message-----
> From: Qiao, Wenjing <wenjing.qiao@intel.com>
> Sent: Friday, April 21, 2023 3:16 PM
> To: Wu, Jingjing <jingjing.wu@intel.com>; Xing, Beilei
> <beilei.xing@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org; Qiao, Wenjing <wenjing.qiao@intel.com>;
> stable@dpdk.org
> Subject: [PATCH v2 2/7] net/idpf: save main time by alarm
>
> Using alarm to save main time from registers every 1 second.
>
> Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
> Cc: stable@dpdk.org
>
> Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
> ---
> drivers/net/idpf/idpf_ethdev.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
> index e02ec2ec5a..3f33ffbc78 100644
> --- a/drivers/net/idpf/idpf_ethdev.c
> +++ b/drivers/net/idpf/idpf_ethdev.c
> @@ -761,6 +761,12 @@ idpf_dev_start(struct rte_eth_dev *dev)
> goto err_vec;
> }
>
> + if (dev->data->dev_conf.rxmode.offloads &
> RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
> + rte_eal_alarm_set(1000 * 1000,
Please use a macro for easy read.
> + &idpf_dev_read_time_hw,
> + (void *)base);
It seems that the alarm logic in the driver/idpf is being continued in common/idpf, which can make the code messy. It would be better to wrap this as internal logic and expose API like "idpf_rx_timestamp_start/stop" in common/idpf for better organization and maintainability.
> + }
> +
> ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
> if (ret != 0) {
> PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
> @@ -810,6 +816,7 @@ static int idpf_dev_stop(struct rte_eth_dev *dev) {
> struct idpf_vport *vport = dev->data->dev_private;
> + struct idpf_adapter *base = vport->adapter;
>
> if (vport->stopped == 1)
> return 0;
> @@ -822,6 +829,11 @@ idpf_dev_stop(struct rte_eth_dev *dev)
>
> idpf_vc_vectors_dealloc(vport);
>
> + if (dev->data->dev_conf.rxmode.offloads &
> RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
> + rte_eal_alarm_cancel(idpf_dev_read_time_hw,
> + base);
> + }
> +
> vport->stopped = 1;
>
> return 0;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* RE: [PATCH v3 6/7] net/cpfl: register timestamp mbuf when starting dev
2023-04-24 9:17 ` [PATCH v3 6/7] net/cpfl: register timestamp mbuf when starting dev Wenjing Qiao
@ 2023-04-28 3:24 ` Zhang, Qi Z
0 siblings, 0 replies; 29+ messages in thread
From: Zhang, Qi Z @ 2023-04-28 3:24 UTC (permalink / raw)
To: Qiao, Wenjing, Wu, Jingjing, Xing, Beilei; +Cc: dev, Liu, Mingxia, stable
> -----Original Message-----
> From: Qiao, Wenjing <wenjing.qiao@intel.com>
> Sent: Monday, April 24, 2023 5:17 PM
> To: Wu, Jingjing <jingjing.wu@intel.com>; Xing, Beilei
> <beilei.xing@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org; Liu, Mingxia <mingxia.liu@intel.com>; Qiao, Wenjing
> <wenjing.qiao@intel.com>; stable@dpdk.org
> Subject: [PATCH v3 6/7] net/cpfl: register timestamp mbuf when starting dev
>
> Due to only support timestamp at port level, registering timestamp mbuf
> should be at dev start stage.
>
> Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
> Cc: stable@dpdk.org
>
> Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
> Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
> ---
> drivers/net/cpfl/cpfl_ethdev.c | 7 +++++++ drivers/net/cpfl/cpfl_ethdev.h |
> 3 +++
> drivers/net/cpfl/cpfl_rxtx.c | 2 ++
> 3 files changed, 12 insertions(+)
>
> diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
> index 82d8147494..416273f567 100644
> --- a/drivers/net/cpfl/cpfl_ethdev.c
> +++ b/drivers/net/cpfl/cpfl_ethdev.c
> @@ -771,6 +771,13 @@ cpfl_dev_start(struct rte_eth_dev *dev)
> rte_eal_alarm_set(1000 * 1000,
> &idpf_dev_read_time_hw,
> (void *)base);
> + /* Register mbuf field and flag for Rx timestamp */
> + ret =
> rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
> +
> &idpf_timestamp_dynflag);
Can we also wrap this into common module, so we don't need to expose idpf_timestamp_dynfield_offset and idpf_timestamp_dynflag which is not used directly by PMD?
> + if (ret != 0) {
> + PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag
> for timestamp");
> + return -EINVAL;
> + }
> }
>
> ret = idpf_vc_vectors_alloc(vport, req_vecs_num); diff --git
> a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h index
> 200dfcac02..eec253bc77 100644
> --- a/drivers/net/cpfl/cpfl_ethdev.h
> +++ b/drivers/net/cpfl/cpfl_ethdev.h
> @@ -57,6 +57,9 @@
> /* Device IDs */
> #define IDPF_DEV_ID_CPF 0x1453
>
> +extern int idpf_timestamp_dynfield_offset; extern uint64_t
> +idpf_timestamp_dynflag;
> +
> struct cpfl_vport_param {
> struct cpfl_adapter_ext *adapter;
> uint16_t devarg_id; /* arg id from user */ diff --git
> a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c index
> de59b31b3d..cdb5b37da0 100644
> --- a/drivers/net/cpfl/cpfl_rxtx.c
> +++ b/drivers/net/cpfl/cpfl_rxtx.c
> @@ -529,6 +529,8 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev,
> uint16_t rx_queue_id)
> frame_size > rxq->rx_buf_len)
> dev->data->scattered_rx = 1;
>
> + if (dev->data->dev_conf.rxmode.offloads &
> RTE_ETH_RX_OFFLOAD_TIMESTAMP)
> + rxq->ts_enable = TRUE;
> err = idpf_qc_ts_mbuf_register(rxq);
> if (err != 0) {
> PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u",
> --
> 2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 1/7] common/idpf: fix 64b timestamp roll over issue
[not found] ` <20230519083110.809913-1-wenjing.qiao@intel.com>
@ 2023-05-19 8:31 ` Wenjing Qiao
2023-05-24 8:36 ` Liu, Mingxia
2023-05-19 8:31 ` [PATCH v4 2/7] net/idpf: save main time by alarm Wenjing Qiao
` (5 subsequent siblings)
6 siblings, 1 reply; 29+ messages in thread
From: Wenjing Qiao @ 2023-05-19 8:31 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
Reading MTS register at first packet will cause timestamp
roll over issue. To support calculating 64b timestamp, need
an alarm to save main time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/common/idpf/idpf_common_rxtx.c | 126 ++++++++++++++-----------
drivers/common/idpf/idpf_common_rxtx.h | 6 +-
drivers/common/idpf/version.map | 2 +
3 files changed, 77 insertions(+), 57 deletions(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index fc87e3e243..b487c2a8a6 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -4,6 +4,7 @@
#include <rte_mbuf_dyn.h>
#include <rte_errno.h>
+#include <rte_alarm.h>
#include "idpf_common_rxtx.h"
@@ -349,6 +350,46 @@ idpf_qc_tx_queue_release(void *txq)
rte_free(q);
}
+#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000
+static void
+idpf_dev_read_time_hw(void *cb_arg)
+{
+#ifdef RTE_ARCH_X86_64
+ struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg;
+ uint32_t hi, lo, lo2;
+ int rc = 0;
+ struct idpf_hw *hw = &ad->hw;
+
+ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
+ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
+ PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
+ lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
+ /*
+ * On typical system, the delta between lo and lo2 is ~1000ns,
+ * so 10000 seems a large-enough but not overly-big guard band.
+ */
+ if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
+ lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ else
+ lo2 = lo;
+
+ if (lo2 < lo) {
+ lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
+ hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
+ }
+
+ ad->time_hw = ((uint64_t)hi << 32) | lo;
+#else /* !RTE_ARCH_X86_64 */
+ ad->time_hw = 0;
+#endif /* RTE_ARCH_X86_64 */
+
+ /* re-alarm watchdog */
+ rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg);
+ if (rc)
+ DRV_LOG(ERR, "Failed to reset device watchdog alarm");
+}
+
int
idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
{
@@ -366,6 +407,24 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
return 0;
}
+
+int
+idpf_rx_timestamp_start(struct idpf_adapter *base)
+{
+ rte_eal_alarm_set(1000 * 1000,
+ &idpf_dev_read_time_hw,
+ (void *)base);
+ return 0;
+}
+
+int
+idpf_rx_timestamp_stop(struct idpf_adapter *base)
+{
+ rte_eal_alarm_cancel(idpf_dev_read_time_hw,
+ base);
+ return 0;
+}
+
int
idpf_qc_single_rxq_mbufs_alloc(struct idpf_rx_queue *rxq)
{
@@ -442,56 +501,23 @@ idpf_qc_split_rxq_mbufs_alloc(struct idpf_rx_queue *rxq)
return 0;
}
-#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000
/* Helper function to convert a 32b nanoseconds timestamp to 64b. */
static inline uint64_t
-idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag,
- uint32_t in_timestamp)
+idpf_tstamp_convert_32b_64b(uint64_t time_hw, uint32_t in_timestamp)
{
-#ifdef RTE_ARCH_X86_64
- struct idpf_hw *hw = &ad->hw;
const uint64_t mask = 0xFFFFFFFF;
- uint32_t hi, lo, lo2, delta;
+ const uint32_t half_overflow_duration = 0x1 << 31;
+ uint32_t delta;
uint64_t ns;
- if (flag != 0) {
- IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
- IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |
- PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
- lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
- /*
- * On typical system, the delta between lo and lo2 is ~1000ns,
- * so 10000 seems a large-enough but not overly-big guard band.
- */
- if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
- lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- else
- lo2 = lo;
-
- if (lo2 < lo) {
- lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
- }
-
- ad->time_hw = ((uint64_t)hi << 32) | lo;
- }
-
- delta = (in_timestamp - (uint32_t)(ad->time_hw & mask));
- if (delta > (mask / 2)) {
- delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);
- ns = ad->time_hw - delta;
+ delta = (in_timestamp - (uint32_t)(time_hw & mask));
+ if (delta > half_overflow_duration) {
+ delta = ((uint32_t)(time_hw & mask) - in_timestamp);
+ ns = time_hw - delta;
} else {
- ns = ad->time_hw + delta;
+ ns = time_hw + delta;
}
-
return ns;
-#else /* !RTE_ARCH_X86_64 */
- RTE_SET_USED(ad);
- RTE_SET_USED(flag);
- RTE_SET_USED(in_timestamp);
- return 0;
-#endif /* RTE_ARCH_X86_64 */
}
#define IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S \
@@ -659,9 +685,6 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
rx_desc_ring = rxq->rx_ring;
ptype_tbl = rxq->adapter->ptype_tbl;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)
- rxq->hw_register_set = 1;
-
while (nb_rx < nb_pkts) {
rx_desc = &rx_desc_ring[rx_id];
@@ -720,10 +743,8 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rx_desc->ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1077,9 +1098,6 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
rx_ring = rxq->rx_ring;
ptype_tbl = rxq->adapter->ptype_tbl;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)
- rxq->hw_register_set = 1;
-
while (nb_rx < nb_pkts) {
rxdp = &rx_ring[rx_id];
rx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0);
@@ -1142,10 +1160,8 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1272,10 +1288,8 @@ idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
- rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h
index 6cb83fc0a6..53049b1a31 100644
--- a/drivers/common/idpf/idpf_common_rxtx.h
+++ b/drivers/common/idpf/idpf_common_rxtx.h
@@ -145,7 +145,6 @@ struct idpf_rx_queue {
struct idpf_rx_queue *bufq2;
uint64_t offloads;
- uint32_t hw_register_set;
};
struct idpf_tx_entry {
@@ -303,4 +302,9 @@ __rte_internal
uint16_t idpf_dp_singleq_recv_scatter_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
+__rte_internal
+int idpf_rx_timestamp_start(struct idpf_adapter *base);
+
+__rte_internal
+int idpf_rx_timestamp_stop(struct idpf_adapter *base);
#endif /* _IDPF_COMMON_RXTX_H_ */
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index 70334a1b03..661c7f5cb9 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -34,6 +34,8 @@ INTERNAL {
idpf_qc_tx_thresh_check;
idpf_qc_tx_vec_avx512_setup;
idpf_qc_txq_mbufs_release;
+ idpf_rx_timestamp_start;
+ idpf_rx_timestamp_stop;
idpf_vc_api_version_check;
idpf_vc_caps_get;
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 2/7] net/idpf: save main time by alarm
[not found] ` <20230519083110.809913-1-wenjing.qiao@intel.com>
2023-05-19 8:31 ` [PATCH v4 " Wenjing Qiao
@ 2023-05-19 8:31 ` Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 3/7] net/cpfl: " Wenjing Qiao
` (4 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-05-19 8:31 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
Using alarm to save main time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/net/idpf/idpf_ethdev.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index 7a33b9eb6a..21f3d0f76a 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -761,6 +761,9 @@ idpf_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ idpf_rx_timestamp_start(base);
+
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
@@ -808,6 +811,7 @@ static int
idpf_dev_stop(struct rte_eth_dev *dev)
{
struct idpf_vport *vport = dev->data->dev_private;
+ struct idpf_adapter *base = vport->adapter;
if (dev->data->dev_started == 0)
return 0;
@@ -820,6 +824,9 @@ idpf_dev_stop(struct rte_eth_dev *dev)
idpf_vc_vectors_dealloc(vport);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ idpf_rx_timestamp_stop(base);
+
return 0;
}
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 3/7] net/cpfl: save main time by alarm
[not found] ` <20230519083110.809913-1-wenjing.qiao@intel.com>
2023-05-19 8:31 ` [PATCH v4 " Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 2/7] net/idpf: save main time by alarm Wenjing Qiao
@ 2023-05-19 8:31 ` Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 4/7] common/idpf: enhance timestamp offload feature for ACC Wenjing Qiao
` (3 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-05-19 8:31 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
Using alarm to save main time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/net/cpfl/cpfl_ethdev.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 7528a14d05..702fd6f4ec 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -767,6 +767,9 @@ cpfl_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ idpf_rx_timestamp_start(base);
+
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
@@ -814,6 +817,7 @@ static int
cpfl_dev_stop(struct rte_eth_dev *dev)
{
struct idpf_vport *vport = dev->data->dev_private;
+ struct idpf_adapter *base = vport->adapter;
if (dev->data->dev_started == 0)
return 0;
@@ -826,6 +830,9 @@ cpfl_dev_stop(struct rte_eth_dev *dev)
idpf_vc_vectors_dealloc(vport);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ idpf_rx_timestamp_stop(base);
+
return 0;
}
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 4/7] common/idpf: enhance timestamp offload feature for ACC
[not found] ` <20230519083110.809913-1-wenjing.qiao@intel.com>
` (2 preceding siblings ...)
2023-05-19 8:31 ` [PATCH v4 3/7] net/cpfl: " Wenjing Qiao
@ 2023-05-19 8:31 ` Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
` (2 subsequent siblings)
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-05-19 8:31 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
For ACC, getting main time from MTS registers by shared memory.
Notice: it is a workaround, and it will be removed after generic
solution are provided.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/common/idpf/base/idpf_osdep.h | 48 ++++++++++++++++++++++++++
drivers/common/idpf/idpf_common_rxtx.c | 30 +++++++++++++---
drivers/common/idpf/meson.build | 2 ++
3 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h
index 2a817a9807..d1668aa603 100644
--- a/drivers/common/idpf/base/idpf_osdep.h
+++ b/drivers/common/idpf/base/idpf_osdep.h
@@ -25,6 +25,13 @@
#include <rte_io.h>
#include <rte_compat.h>
+#ifdef IDPF_ACC_TIMESTAMP
+#include <stdio.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <sys/mman.h>
+#endif /* IDPF_ACC_TIMESTAMP */
+
#define INLINE inline
#define STATIC static
@@ -346,4 +353,45 @@ idpf_hweight32(u32 num)
#endif
+#ifdef IDPF_ACC_TIMESTAMP
+#define IDPF_ACC_TIMESYNC_BASE_ADDR 0x480D500000
+#define IDPF_ACC_GLTSYN_TIME_H (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x1C)
+#define IDPF_ACC_GLTSYN_TIME_L (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x10)
+
+inline uint32_t
+idpf_mmap_r32(uint64_t pa)
+{
+ int fd;
+ void *bp, *vp;
+ uint32_t rval = 0xdeadbeef;
+ uint32_t ps, ml, of;
+
+ fd = open("/dev/mem", (O_RDWR | O_SYNC));
+ if (fd == -1) {
+ perror("/dev/mem");
+ return -1;
+ }
+ ml = ps = getpagesize();
+ of = (uint32_t)pa & (ps - 1);
+ if (of + (sizeof(uint32_t) * 4) > ps)
+ ml *= 2;
+ bp = mmap(NULL, ml, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, pa & ~(uint64_t)(ps - 1));
+ if (bp == MAP_FAILED) {
+ perror("mmap");
+ goto done;
+ }
+
+ vp = (char *)bp + of;
+
+ rval = *(volatile uint32_t *)vp;
+ if (munmap(bp, ml) == -1)
+ perror("munmap");
+done:
+ close(fd);
+
+ return rval;
+}
+
+#endif /* IDPF_ACC_TIMESTAMP */
+
#endif /* _IDPF_OSDEP_H_ */
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index b487c2a8a6..13e94dda43 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -354,12 +354,36 @@ idpf_qc_tx_queue_release(void *txq)
static void
idpf_dev_read_time_hw(void *cb_arg)
{
-#ifdef RTE_ARCH_X86_64
struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg;
uint32_t hi, lo, lo2;
int rc = 0;
+#ifndef IDPF_ACC_TIMESTAMP
struct idpf_hw *hw = &ad->hw;
+#endif /* !IDPF_ACC_TIMESTAMP */
+#ifdef IDPF_ACC_TIMESTAMP
+
+ lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);
+ hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H);
+ DRV_LOG(DEBUG, "lo : %X,", lo);
+ DRV_LOG(DEBUG, "hi : %X,", hi);
+ /*
+ * On typical system, the delta between lo and lo2 is ~1000ns,
+ * so 10000 seems a large-enough but not overly-big guard band.
+ */
+ if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
+ lo2 = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);
+ else
+ lo2 = lo;
+
+ if (lo2 < lo) {
+ lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);
+ hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H);
+ }
+
+ ad->time_hw = ((uint64_t)hi << 32) | lo;
+
+#else /* !IDPF_ACC_TIMESTAMP */
IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
@@ -380,9 +404,7 @@ idpf_dev_read_time_hw(void *cb_arg)
}
ad->time_hw = ((uint64_t)hi << 32) | lo;
-#else /* !RTE_ARCH_X86_64 */
- ad->time_hw = 0;
-#endif /* RTE_ARCH_X86_64 */
+#endif /* IDPF_ACC_TIMESTAMP */
/* re-alarm watchdog */
rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg);
diff --git a/drivers/common/idpf/meson.build b/drivers/common/idpf/meson.build
index 80c8906f80..11682a27d5 100644
--- a/drivers/common/idpf/meson.build
+++ b/drivers/common/idpf/meson.build
@@ -45,3 +45,5 @@ if arch_subdir == 'x86'
endif
subdir('base')
+
+ dpdk_conf.set('IDPF_ACC_TIMESTAMP', false)
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 5/7] common/idpf: add timestamp enable flag for rxq
[not found] ` <20230519083110.809913-1-wenjing.qiao@intel.com>
` (3 preceding siblings ...)
2023-05-19 8:31 ` [PATCH v4 4/7] common/idpf: enhance timestamp offload feature for ACC Wenjing Qiao
@ 2023-05-19 8:31 ` Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 6/7] net/cpfl: adjust timestamp mbuf register Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 7/7] net/idpf: " Wenjing Qiao
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-05-19 8:31 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
A rxq can be configured with timestamp offload.
So, add timestamp enable flag for rxq.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/common/idpf/idpf_common_rxtx.c | 11 ++++++++++-
drivers/common/idpf/idpf_common_rxtx.h | 2 ++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c
index 13e94dda43..26aaddb106 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -416,7 +416,7 @@ int
idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
{
int err;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
+ if (!rxq->ts_enable && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {
/* Register mbuf field and flag for Rx timestamp */
err = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
&idpf_timestamp_dynflag);
@@ -425,6 +425,7 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
"Cannot register mbuf field/flag for timestamp");
return -EINVAL;
}
+ rxq->ts_enable = TRUE;
}
return 0;
}
@@ -433,9 +434,17 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
int
idpf_rx_timestamp_start(struct idpf_adapter *base)
{
+ int ret;
rte_eal_alarm_set(1000 * 1000,
&idpf_dev_read_time_hw,
(void *)base);
+ /* Register mbuf field and flag for Rx timestamp */
+ ret = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
+ &idpf_timestamp_dynflag);
+ if (ret != 0) {
+ DRV_LOG(ERR, "Cannot register mbuf field/flag for timestamp");
+ return -EINVAL;
+ }
return 0;
}
diff --git a/drivers/common/idpf/idpf_common_rxtx.h b/drivers/common/idpf/idpf_common_rxtx.h
index 53049b1a31..e902c4f275 100644
--- a/drivers/common/idpf/idpf_common_rxtx.h
+++ b/drivers/common/idpf/idpf_common_rxtx.h
@@ -145,6 +145,8 @@ struct idpf_rx_queue {
struct idpf_rx_queue *bufq2;
uint64_t offloads;
+
+ bool ts_enable; /* if timestamp is enabled */
};
struct idpf_tx_entry {
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 6/7] net/cpfl: adjust timestamp mbuf register
[not found] ` <20230519083110.809913-1-wenjing.qiao@intel.com>
` (4 preceding siblings ...)
2023-05-19 8:31 ` [PATCH v4 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
@ 2023-05-19 8:31 ` Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 7/7] net/idpf: " Wenjing Qiao
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-05-19 8:31 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
Due to only support timestamp at port level, adjust
timestamp mbuf register to dev config.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/cpfl/cpfl_ethdev.c | 9 +++++++--
drivers/net/cpfl/cpfl_rxtx.c | 2 ++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 702fd6f4ec..a6a17d03f9 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -767,8 +767,13 @@ cpfl_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
- if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
- idpf_rx_timestamp_start(base);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ ret = idpf_rx_timestamp_start(base);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Failed to register mbuf for timestamp");
+ goto err_vec;
+ }
+ }
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c
index 75021c3c54..4781059f2c 100644
--- a/drivers/net/cpfl/cpfl_rxtx.c
+++ b/drivers/net/cpfl/cpfl_rxtx.c
@@ -530,6 +530,8 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)
frame_size > rxq->rx_buf_len)
dev->data->scattered_rx = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ rxq->ts_enable = TRUE;
err = idpf_qc_ts_mbuf_register(rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u",
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v4 7/7] net/idpf: adjust timestamp mbuf register
[not found] ` <20230519083110.809913-1-wenjing.qiao@intel.com>
` (5 preceding siblings ...)
2023-05-19 8:31 ` [PATCH v4 6/7] net/cpfl: adjust timestamp mbuf register Wenjing Qiao
@ 2023-05-19 8:31 ` Wenjing Qiao
6 siblings, 0 replies; 29+ messages in thread
From: Wenjing Qiao @ 2023-05-19 8:31 UTC (permalink / raw)
To: jingjing.wu, beilei.xing, qi.z.zhang
Cc: dev, mingxia.liu, Wenjing Qiao, stable
Due to only support timestamp at port level, adjust
timestamp mbuf register to dev config.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
Suggested-by: Jingjing Wu <jingjing.wu@intel.com>
---
drivers/net/idpf/idpf_ethdev.c | 9 +++++++--
drivers/net/idpf/idpf_rxtx.c | 3 +++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index 21f3d0f76a..18c5844adb 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -761,8 +761,13 @@ idpf_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
- if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
- idpf_rx_timestamp_start(base);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
+ ret = idpf_rx_timestamp_start(base);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Failed to register mbuf for timestamp");
+ goto err_vec;
+ }
+ }
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
diff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c
index 3e3d81ca6d..6c893c64a8 100644
--- a/drivers/net/idpf/idpf_rxtx.c
+++ b/drivers/net/idpf/idpf_rxtx.c
@@ -531,6 +531,9 @@ idpf_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)
frame_size > rxq->rx_buf_len)
dev->data->scattered_rx = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ rxq->ts_enable = TRUE;
+
err = idpf_qc_ts_mbuf_register(rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "fail to residter timestamp mbuf %u",
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* RE: [PATCH v4 1/7] common/idpf: fix 64b timestamp roll over issue
2023-05-19 8:31 ` [PATCH v4 " Wenjing Qiao
@ 2023-05-24 8:36 ` Liu, Mingxia
0 siblings, 0 replies; 29+ messages in thread
From: Liu, Mingxia @ 2023-05-24 8:36 UTC (permalink / raw)
To: Qiao, Wenjing, Wu, Jingjing, Xing, Beilei, Zhang, Qi Z; +Cc: dev, stable
> -----Original Message-----
> From: Qiao, Wenjing <wenjing.qiao@intel.com>
> Sent: Friday, May 19, 2023 4:31 PM
> To: Wu, Jingjing <jingjing.wu@intel.com>; Xing, Beilei <beilei.xing@intel.com>;
> Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org; Liu, Mingxia <mingxia.liu@intel.com>; Qiao, Wenjing
> <wenjing.qiao@intel.com>; stable@dpdk.org
> Subject: [PATCH v4 1/7] common/idpf: fix 64b timestamp roll over issue
>
> Reading MTS register at first packet will cause timestamp roll over issue. To
> support calculating 64b timestamp, need an alarm to save main time from
> registers every 1 second.
>
> Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
> Cc: stable@dpdk.org
>
> Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
> ---
> drivers/common/idpf/idpf_common_rxtx.c | 126 ++++++++++++++-----------
> drivers/common/idpf/idpf_common_rxtx.h | 6 +-
> drivers/common/idpf/version.map | 2 +
> 3 files changed, 77 insertions(+), 57 deletions(-)
>
> diff --git a/drivers/common/idpf/idpf_common_rxtx.c
> b/drivers/common/idpf/idpf_common_rxtx.c
> index fc87e3e243..b487c2a8a6 100644
> --- a/drivers/common/idpf/idpf_common_rxtx.c
> +++ b/drivers/common/idpf/idpf_common_rxtx.c
> @@ -4,6 +4,7 @@
/* re-alarm watchdog */
> + rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg);
...
> +int
> +idpf_rx_timestamp_start(struct idpf_adapter *base) {
> + rte_eal_alarm_set(1000 * 1000,
> + &idpf_dev_read_time_hw,
> + (void *)base);
> + return 0;
> +}
> +
[Liu, Mingxia] 1000*1000us means 1s, better to use macro variables, such as "US_PER_S", will be more readable.
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2023-05-24 8:37 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20230420091935.43116-1-wenjing.qiao@intel.com>
2023-04-20 9:19 ` [PATCH 1/7] common/idpf: fix 64b timestamp roll over issue Wenjing Qiao
[not found] ` <20230421071603.55680-1-wenjing.qiao@intel.com>
2023-04-21 7:15 ` [PATCH v2 " Wenjing Qiao
[not found] ` <20230424091707.488045-1-wenjing.qiao@intel.com>
2023-04-24 9:17 ` [PATCH v3 " Wenjing Qiao
[not found] ` <20230519083110.809913-1-wenjing.qiao@intel.com>
2023-05-19 8:31 ` [PATCH v4 " Wenjing Qiao
2023-05-24 8:36 ` Liu, Mingxia
2023-05-19 8:31 ` [PATCH v4 2/7] net/idpf: save main time by alarm Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 3/7] net/cpfl: " Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 4/7] common/idpf: enhance timestamp offload feature for ACC Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 6/7] net/cpfl: adjust timestamp mbuf register Wenjing Qiao
2023-05-19 8:31 ` [PATCH v4 7/7] net/idpf: " Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 2/7] net/idpf: save main time by alarm Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 3/7] net/cpfl: " Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 4/7] common/idpf: enhance timestamp offload feature for ACC Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
2023-04-24 9:17 ` [PATCH v3 6/7] net/cpfl: register timestamp mbuf when starting dev Wenjing Qiao
2023-04-28 3:24 ` Zhang, Qi Z
2023-04-24 9:17 ` [PATCH v3 7/7] net/idpf: " Wenjing Qiao
2023-04-21 7:15 ` [PATCH v2 2/7] net/idpf: save main time by alarm Wenjing Qiao
2023-04-28 2:46 ` Zhang, Qi Z
2023-04-21 7:15 ` [PATCH v2 3/7] net/cpfl: " Wenjing Qiao
2023-04-21 7:16 ` [PATCH v2 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
2023-04-21 7:16 ` [PATCH v2 6/7] net/cpfl: register timestamp mbuf when starting dev Wenjing Qiao
2023-04-21 7:16 ` [PATCH v2 7/7] net/idpf: " Wenjing Qiao
2023-04-20 9:19 ` [PATCH 2/7] net/idpf: save master time by alarm Wenjing Qiao
2023-04-20 9:19 ` [PATCH 3/7] net/cpfl: " Wenjing Qiao
2023-04-20 9:19 ` [PATCH 5/7] common/idpf: add timestamp enable flag for rxq Wenjing Qiao
2023-04-20 9:19 ` [PATCH 6/7] net/cpfl: register timestamp mbuf when starting dev Wenjing Qiao
2023-04-20 9:19 ` [PATCH 7/7] net/idpf: " Wenjing Qiao
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).