From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B8B08429D9 for ; Mon, 24 Apr 2023 11:23:04 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 73F8942D3A; Mon, 24 Apr 2023 11:23:02 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id C89CC42D31; Mon, 24 Apr 2023 11:22:59 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682328180; x=1713864180; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D1xeMQBK3/UBoW/17IB/HQbbUD/ywjtGem9EljSzqaU=; b=E86t9ueB+4fMuN/nAl+ThlhqZXO/e87vicUx9C2O7i7U4HcnCHFAWzwh MOVYRXAg+zFJhL+B2dkbWrBZk6jmDLCvYX01xZKfzbzTgx2/qqD6cl2sI cNGF024fdGdHXHO+h48rHl2gOFboUCJoDThl0LZmQRKILnxqWcMVdiB7d Eaa0GSaP2icIPuSk9hk8e8U7ciGeZHfj/n4zjxBNFiDGEAjoxG2VAbNJB C465BPZy7m3sWCepqJ6mWFdoJ8vYfS4DgCeFbsJjBdKYqL/GUiRU/XZ7b dwPfsIuw6hD1v0a8CpFr+nmXBHdMVz6mfebunwOF019Ghog2K6+8DTwL5 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="411680065" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="411680065" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2023 02:22:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10689"; a="836895091" X-IronPort-AV: E=Sophos;i="5.99,222,1677571200"; d="scan'208";a="836895091" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga001.fm.intel.com with ESMTP; 24 Apr 2023 02:22:57 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , stable@dpdk.org Subject: [PATCH v3 4/7] common/idpf: enhance timestamp offload feature for ACC Date: Mon, 24 Apr 2023 05:17:04 -0400 Message-Id: <20230424091707.488045-5-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424091707.488045-1-wenjing.qiao@intel.com> References: <20230421071603.55680-2-wenjing.qiao@intel.com> <20230424091707.488045-1-wenjing.qiao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org For ACC, getting main time from MTS registers by shared memory. Notice: it is a workaround, and it will be removed after generic solution are provided. Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path") Cc: stable@dpdk.org Signed-off-by: Wenjing Qiao --- config/meson.build | 3 ++ drivers/common/idpf/base/idpf_osdep.h | 48 ++++++++++++++++++++++++++ drivers/common/idpf/idpf_common_rxtx.c | 30 +++++++++++++--- meson_options.txt | 2 ++ 4 files changed, 79 insertions(+), 4 deletions(-) diff --git a/config/meson.build b/config/meson.build index fa730a1b14..8d74f301b4 100644 --- a/config/meson.build +++ b/config/meson.build @@ -316,6 +316,9 @@ endif if get_option('mbuf_refcnt_atomic') dpdk_conf.set('RTE_MBUF_REFCNT_ATOMIC', true) endif +if get_option('enable_acc_timestamp') + dpdk_conf.set('IDPF_ACC_TIMESTAMP', true) +endif dpdk_conf.set10('RTE_IOVA_IN_MBUF', get_option('enable_iova_as_pa')) compile_time_cpuflags = [] diff --git a/drivers/common/idpf/base/idpf_osdep.h b/drivers/common/idpf/base/idpf_osdep.h index 99ae9cf60a..e634939a51 100644 --- a/drivers/common/idpf/base/idpf_osdep.h +++ b/drivers/common/idpf/base/idpf_osdep.h @@ -24,6 +24,13 @@ #include #include +#ifdef IDPF_ACC_TIMESTAMP +#include +#include +#include +#include +#endif /* IDPF_ACC_TIMESTAMP */ + #define INLINE inline #define STATIC static @@ -361,4 +368,45 @@ idpf_hweight32(u32 num) #endif +#ifdef IDPF_ACC_TIMESTAMP +#define IDPF_ACC_TIMESYNC_BASE_ADDR 0x480D500000 +#define IDPF_ACC_GLTSYN_TIME_H (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x1C) +#define IDPF_ACC_GLTSYN_TIME_L (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x10) + +inline uint32_t +idpf_mmap_r32(uint64_t pa) +{ + int fd; + void *bp, *vp; + uint32_t rval = 0xdeadbeef; + uint32_t ps, ml, of; + + fd = open("/dev/mem", (O_RDWR | O_SYNC)); + if (fd == -1) { + perror("/dev/mem"); + return -1; + } + ml = ps = getpagesize(); + of = (uint32_t)pa & (ps - 1); + if (of + (sizeof(uint32_t) * 4) > ps) + ml *= 2; + bp = mmap(NULL, ml, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, pa & ~(uint64_t)(ps - 1)); + if (bp == MAP_FAILED) { + perror("mmap"); + goto done; + } + + vp = (char *)bp + of; + + rval = *(volatile uint32_t *)vp; + if (munmap(bp, ml) == -1) + perror("munmap"); +done: + close(fd); + + return rval; +} + +#endif /* IDPF_ACC_TIMESTAMP */ + #endif /* _IDPF_OSDEP_H_ */ diff --git a/drivers/common/idpf/idpf_common_rxtx.c b/drivers/common/idpf/idpf_common_rxtx.c index 19bcb94077..9c58f3fb11 100644 --- a/drivers/common/idpf/idpf_common_rxtx.c +++ b/drivers/common/idpf/idpf_common_rxtx.c @@ -1582,12 +1582,36 @@ idpf_qc_splitq_rx_vec_setup(struct idpf_rx_queue *rxq) void idpf_dev_read_time_hw(void *cb_arg) { -#ifdef RTE_ARCH_X86_64 struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg; uint32_t hi, lo, lo2; int rc = 0; +#ifndef IDPF_ACC_TIMESTAMP struct idpf_hw *hw = &ad->hw; +#endif /* !IDPF_ACC_TIMESTAMP */ +#ifdef IDPF_ACC_TIMESTAMP + + lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L); + hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H); + DRV_LOG(DEBUG, "lo : %X,", lo); + DRV_LOG(DEBUG, "hi : %X,", hi); + /* + * On typical system, the delta between lo and lo2 is ~1000ns, + * so 10000 seems a large-enough but not overly-big guard band. + */ + if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND)) + lo2 = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L); + else + lo2 = lo; + + if (lo2 < lo) { + lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L); + hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H); + } + + ad->time_hw = ((uint64_t)hi << 32) | lo; + +#else /* !IDPF_ACC_TIMESTAMP */ IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M | PF_GLTSYN_CMD_SYNC_SHTIME_EN_M); @@ -1608,9 +1632,7 @@ idpf_dev_read_time_hw(void *cb_arg) } ad->time_hw = ((uint64_t)hi << 32) | lo; -#else /* !RTE_ARCH_X86_64 */ - ad->time_hw = 0; -#endif /* RTE_ARCH_X86_64 */ +#endif /* IDPF_ACC_TIMESTAMP */ /* re-alarm watchdog */ rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg); diff --git a/meson_options.txt b/meson_options.txt index 82c8297065..31fc634aa0 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -52,3 +52,5 @@ option('tests', type: 'boolean', value: true, description: 'build unit tests') option('use_hpet', type: 'boolean', value: false, description: 'use HPET timer in EAL') +option('enable_acc_timestamp', type: 'boolean', value: false, description: + 'enable timestamp on ACC.') -- 2.25.1