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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DM6NAM11FT017.mail.protection.outlook.com (10.13.172.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.20 via Frontend Transport; Tue, 2 May 2023 18:51:13 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 2 May 2023 11:51:02 -0700 Received: from pegasus01.mtr.labs.mlnx (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 2 May 2023 11:51:00 -0700 From: Alexander Kozyrev To: CC: , , , Subject: [PATCH] drivers: ignore non-critical syndromes for Tx queues Date: Tue, 2 May 2023 21:50:47 +0300 Message-ID: <20230502185047.3250224-1-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT017:EE_|DM4PR12MB7646:EE_ X-MS-Office365-Filtering-Correlation-Id: 64e90393-ec41-4600-5bec-08db4b3e343d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 18:51:13.8143 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64e90393-ec41-4600-5bec-08db4b3e343d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7646 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Only 3 syndromes are considered critical and warrant a queue restart. All other syndromes can be safely ignored. We ignore them for Rx queues. Skip non-critical error CQEs for Tx queues as well. Fixes: 957e45fb7b ("net/mlx5: handle Tx completion with error") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev --- drivers/common/mlx5/mlx5_prm.h | 17 +++++++++++++++++ drivers/net/mlx5/mlx5_rx.c | 4 +--- drivers/net/mlx5/mlx5_tx.c | 4 ++-- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 505ff3cc8e..93bcb5e4b7 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -5265,4 +5265,21 @@ mlx5_ts_format_conv(uint32_t ts_format) MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; } +/** + * Check if an error CQE syndrome is critical. + * + * @param syndrome + * Error CQE syndrome to check. + * + * @return + * Positive value if critical, 0 otherwise. + */ +static inline uint32_t +mlx5_critical_syndrome(uint8_t syndrome) +{ + return (syndrome == MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR || + syndrome == MLX5_CQE_SYNDROME_LOCAL_PROT_ERR || + syndrome == MLX5_CQE_SYNDROME_WR_FLUSH_ERR); +} + #endif /* RTE_PMD_MLX5_PRM_H_ */ diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index 69fd173239..72c6eeac42 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -479,9 +479,7 @@ mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec, for (i = 0; i < (int)err_n; i++) { u.cqe = &(*rxq->cqes)[(rxq->cq_ci - vec - i) & cqe_mask]; if (MLX5_CQE_OPCODE(u.cqe->op_own) == MLX5_CQE_RESP_ERR) { - if (u.err_cqe->syndrome == MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR || - u.err_cqe->syndrome == MLX5_CQE_SYNDROME_LOCAL_PROT_ERR || - u.err_cqe->syndrome == MLX5_CQE_SYNDROME_WR_FLUSH_ERR) + if (mlx5_critical_syndrome(u.err_cqe->syndrome)) critical_syndrome = true; break; } diff --git a/drivers/net/mlx5/mlx5_tx.c b/drivers/net/mlx5/mlx5_tx.c index 8b1a0ca3d3..1e6766bd84 100644 --- a/drivers/net/mlx5/mlx5_tx.c +++ b/drivers/net/mlx5/mlx5_tx.c @@ -85,7 +85,7 @@ static int mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq, volatile struct mlx5_error_cqe *err_cqe) { - if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) { + if (mlx5_critical_syndrome(err_cqe->syndrome)) { const uint16_t wqe_m = ((1 << txq->wqe_n) - 1); struct mlx5_txq_ctrl *txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); @@ -217,7 +217,7 @@ mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq, } /* * We are going to fetch all entries with - * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status. + * non-critical error syndromes. * The send queue is supposed to be empty. */ ring_doorbell = true; -- 2.18.2