From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4B8C642C40 for ; Tue, 6 Jun 2023 14:13:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 44EFD410DD; Tue, 6 Jun 2023 14:13:08 +0200 (CEST) Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by mails.dpdk.org (Postfix) with ESMTP id 4DA3E40223; Tue, 6 Jun 2023 14:13:04 +0200 (CEST) Received: from kwepemi500017.china.huawei.com (unknown [172.30.72.55]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4Qb8Pn5vzxz18M3Y; Tue, 6 Jun 2023 20:08:13 +0800 (CST) Received: from localhost.localdomain (10.28.79.22) by kwepemi500017.china.huawei.com (7.221.188.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Tue, 6 Jun 2023 20:12:59 +0800 From: Dongdong Liu To: , , , CC: , Subject: [PATCH] net/hns3: fix the way to trigger IMP reset Date: Tue, 6 Jun 2023 20:10:28 +0800 Message-ID: <20230606121028.9644-1-liudongdong3@huawei.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.28.79.22] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500017.china.huawei.com (7.221.188.110) X-CFilter-Loop: Reflected X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org From: Huisong Li Currently, driver sends the command with an unknown opcode to the firmware to trigger IMP reset when some hardware error happened. This unknown opcode cannot be parsed by the firmware. So this patch fixes the way by writing register to do it. Fixes: 2790c6464725 ("net/hns3: support device reset") Cc: stable@dpdk.org Signed-off-by: Huisong Li Signed-off-by: Dongdong Liu --- drivers/net/hns3/hns3_ethdev.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index dccd1d416f..95c72e86aa 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -44,6 +44,7 @@ #define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U #define HNS3_VECTOR0_IMP_RD_POISON_B 5U #define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U +#define HNS3_VECTOR0_TRIGGER_IMP_RESET_B 7U #define HNS3_RESET_WAIT_MS 100 #define HNS3_RESET_WAIT_CNT 200 @@ -5575,17 +5576,6 @@ hns3_func_reset_cmd(struct hns3_hw *hw, int func_id) return hns3_cmd_send(hw, &desc, 1); } -static int -hns3_imp_reset_cmd(struct hns3_hw *hw) -{ - struct hns3_cmd_desc desc; - - hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false); - desc.data[0] = 0xeedd; - - return hns3_cmd_send(hw, &desc, 1); -} - static void hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) { @@ -5603,7 +5593,9 @@ hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level) switch (reset_level) { case HNS3_IMP_RESET: - hns3_imp_reset_cmd(hw); + val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG); + hns3_set_bit(val, HNS3_VECTOR0_TRIGGER_IMP_RESET_B, 1); + hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val); hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld", tv.tv_sec, tv.tv_usec); break; -- 2.22.0