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From: Junfeng Guo <junfeng.guo@intel.com>
To: jingjing.wu@intel.com
Cc: dev@dpdk.org,
stable@dpdk.org,
Junfeng Guo <junfeng.guo@intel.com>
Subject: [PATCH] doc: update BIOS setting and supported HW list for NTB
Date: Mon, 3 Jul 2023 17:24:34 +0800
Message-Id: <20230703092434.3424624-1-junfeng.guo@intel.com>
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Update BIOS settings and supported platform list for Intel NTB.
Fixes: f5057be340e4 ("raw/ntb: support Intel Ice Lake")
Cc: stable@dpdk.org
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
---
doc/guides/rawdevs/ntb.rst | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/doc/guides/rawdevs/ntb.rst b/doc/guides/rawdevs/ntb.rst
index 2bb115d13f..c34512177a 100644
--- a/doc/guides/rawdevs/ntb.rst
+++ b/doc/guides/rawdevs/ntb.rst
@@ -17,18 +17,22 @@ some information by using scratchpad registers.
BIOS setting on Intel Xeon
--------------------------
-Intel Non-transparent Bridge needs special BIOS setting. The reference for
-Skylake is https://www.intel.com/content/dam/support/us/en/documents/server-products/Intel_Xeon_Processor_Scalable_Family_BIOS_User_Guide.pdf
-
-- Set the needed PCIe port as NTB to NTB mode on both hosts.
-- Enable NTB bars and set bar size of bar 23 and bar 45 as 12-29 (4K-512M)
- on both hosts (for Ice Lake, bar size can be set as 12-51, namely 4K-128PB).
- Note that bar size on both hosts should be the same.
-- Disable split bars for both hosts.
-- Set crosslink control override as DSD/USP on one host, USD/DSP on
+Intel Non-transparent Bridge (NTB) needs special BIOS settings on both systems.
+Note that for 4th Generation Intel® Xeon® Scalable Processors, option ``Port
+Subsystem Mode`` should be changed from ``Gen5`` to ``Gen4 Only``, then reboot.
+
+- Set ``Non-Transparent Bridge PCIe Port Definition`` for needed PCIe ports as
+ ``NTB to NTB`` mode, on both hosts.
+- Set ``Enable NTB BARs`` as ``Enabled``, on both hosts.
+- Set ``Enable SPLIT BARs`` as ``Disabled``, on both hosts.
+- Set ``Imbar1 Size``, ``Imbar2 Size``, ``Embar1 Size`` and ``Embar2 Size``, as
+ 12-29 (i.e., 4K-512M) for 2nd Generation Intel® Xeon® Scalable Processors; as
+ 12-51 (i.e., 4K-128PB) for 3rd and 4th Generation Intel® Xeon® Scalable
+ Processors. Note that those bar sizes on both hosts should be the same.
+- Set ``Crosslink Control override`` as ``DSD/USP`` on one host, ``USD/DSP`` on
another host.
-- Disable PCIe PII SSC (Spread Spectrum Clocking) for both hosts. This
- is a hardware requirement.
+- Set ``PCIe PLL SSC (Spread Spectrum Clocking)`` as ``Disabled``, on both
+ hosts. This is a hardware requirement when using Re-timer Cards.
Device Setup
@@ -145,4 +149,8 @@ like the following:
Limitation
----------
-- This PMD only supports Intel Skylake and Ice Lake platforms.
+This PMD is only supported on Intel Xeon Platforms:
+
+- 4th Generation Intel® Xeon® Scalable Processors.
+- 3rd Generation Intel® Xeon® Scalable Processors.
+- 2nd Generation Intel® Xeon® Scalable Processors.
--
2.34.1