From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6D1BA42DAE for ; Mon, 3 Jul 2023 11:24:48 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 64D9041151; Mon, 3 Jul 2023 11:24:48 +0200 (CEST) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 813BF40156; Mon, 3 Jul 2023 11:24:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1688376285; x=1719912285; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=9pVzrTnohk6f0ugKUNqLQ8xBmoCbHLTXYpyJ4sTuTJw=; b=Bh1YG4kDAihVgn6jUTJ2PDnfUSmM+oTLIUaT9ImQ1YDTRbXWxJVlaODJ lddPRaTFYEGYEDftS0uo68J53bs/zhx2D/fCnMuO98cE5hz+1ucnp3ERj VY+PazKJiAXgnjqiOkZOJXZfFYUjL8RDpUOuDZBGl+w6N+k4zP0pgFhQ/ 1rpr+p32GHxlCoLnPPK/L5i81Z/XA6vtrJUTSSpF1F8vXz40XHjpWvUQu 9oKYFyJuH2koVziNTIGn+S14iidAH4bGuk1wj4zl81FqMJp+GKZcscdy2 iBTA/Y47ljlCechCiJ+4BS4/dr9hLXBhjeNwP0xpxNsVTNACCaU9REyAT A==; X-IronPort-AV: E=McAfee;i="6600,9927,10759"; a="426521277" X-IronPort-AV: E=Sophos;i="6.01,177,1684825200"; d="scan'208";a="426521277" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2023 02:24:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10759"; a="1049012298" X-IronPort-AV: E=Sophos;i="6.01,177,1684825200"; d="scan'208";a="1049012298" Received: from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.149]) by fmsmga005.fm.intel.com with ESMTP; 03 Jul 2023 02:24:42 -0700 From: Junfeng Guo To: jingjing.wu@intel.com Cc: dev@dpdk.org, stable@dpdk.org, Junfeng Guo Subject: [PATCH] doc: update BIOS setting and supported HW list for NTB Date: Mon, 3 Jul 2023 17:24:34 +0800 Message-Id: <20230703092434.3424624-1-junfeng.guo@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Update BIOS settings and supported platform list for Intel NTB. Fixes: f5057be340e4 ("raw/ntb: support Intel Ice Lake") Cc: stable@dpdk.org Signed-off-by: Junfeng Guo --- doc/guides/rawdevs/ntb.rst | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/doc/guides/rawdevs/ntb.rst b/doc/guides/rawdevs/ntb.rst index 2bb115d13f..c34512177a 100644 --- a/doc/guides/rawdevs/ntb.rst +++ b/doc/guides/rawdevs/ntb.rst @@ -17,18 +17,22 @@ some information by using scratchpad registers. BIOS setting on Intel Xeon -------------------------- -Intel Non-transparent Bridge needs special BIOS setting. The reference for -Skylake is https://www.intel.com/content/dam/support/us/en/documents/server-products/Intel_Xeon_Processor_Scalable_Family_BIOS_User_Guide.pdf - -- Set the needed PCIe port as NTB to NTB mode on both hosts. -- Enable NTB bars and set bar size of bar 23 and bar 45 as 12-29 (4K-512M) - on both hosts (for Ice Lake, bar size can be set as 12-51, namely 4K-128PB). - Note that bar size on both hosts should be the same. -- Disable split bars for both hosts. -- Set crosslink control override as DSD/USP on one host, USD/DSP on +Intel Non-transparent Bridge (NTB) needs special BIOS settings on both systems. +Note that for 4th Generation Intel® Xeon® Scalable Processors, option ``Port +Subsystem Mode`` should be changed from ``Gen5`` to ``Gen4 Only``, then reboot. + +- Set ``Non-Transparent Bridge PCIe Port Definition`` for needed PCIe ports as + ``NTB to NTB`` mode, on both hosts. +- Set ``Enable NTB BARs`` as ``Enabled``, on both hosts. +- Set ``Enable SPLIT BARs`` as ``Disabled``, on both hosts. +- Set ``Imbar1 Size``, ``Imbar2 Size``, ``Embar1 Size`` and ``Embar2 Size``, as + 12-29 (i.e., 4K-512M) for 2nd Generation Intel® Xeon® Scalable Processors; as + 12-51 (i.e., 4K-128PB) for 3rd and 4th Generation Intel® Xeon® Scalable + Processors. Note that those bar sizes on both hosts should be the same. +- Set ``Crosslink Control override`` as ``DSD/USP`` on one host, ``USD/DSP`` on another host. -- Disable PCIe PII SSC (Spread Spectrum Clocking) for both hosts. This - is a hardware requirement. +- Set ``PCIe PLL SSC (Spread Spectrum Clocking)`` as ``Disabled``, on both + hosts. This is a hardware requirement when using Re-timer Cards. Device Setup @@ -145,4 +149,8 @@ like the following: Limitation ---------- -- This PMD only supports Intel Skylake and Ice Lake platforms. +This PMD is only supported on Intel Xeon Platforms: + +- 4th Generation Intel® Xeon® Scalable Processors. +- 3rd Generation Intel® Xeon® Scalable Processors. +- 2nd Generation Intel® Xeon® Scalable Processors. -- 2.34.1