* [PATCH] doc: update BIOS setting and supported HW list for NTB
@ 2023-07-03 9:24 Junfeng Guo
2023-07-03 9:35 ` Wu, Jingjing
0 siblings, 1 reply; 6+ messages in thread
From: Junfeng Guo @ 2023-07-03 9:24 UTC (permalink / raw)
To: jingjing.wu; +Cc: dev, stable, Junfeng Guo
Update BIOS settings and supported platform list for Intel NTB.
Fixes: f5057be340e4 ("raw/ntb: support Intel Ice Lake")
Cc: stable@dpdk.org
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
---
doc/guides/rawdevs/ntb.rst | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/doc/guides/rawdevs/ntb.rst b/doc/guides/rawdevs/ntb.rst
index 2bb115d13f..c34512177a 100644
--- a/doc/guides/rawdevs/ntb.rst
+++ b/doc/guides/rawdevs/ntb.rst
@@ -17,18 +17,22 @@ some information by using scratchpad registers.
BIOS setting on Intel Xeon
--------------------------
-Intel Non-transparent Bridge needs special BIOS setting. The reference for
-Skylake is https://www.intel.com/content/dam/support/us/en/documents/server-products/Intel_Xeon_Processor_Scalable_Family_BIOS_User_Guide.pdf
-
-- Set the needed PCIe port as NTB to NTB mode on both hosts.
-- Enable NTB bars and set bar size of bar 23 and bar 45 as 12-29 (4K-512M)
- on both hosts (for Ice Lake, bar size can be set as 12-51, namely 4K-128PB).
- Note that bar size on both hosts should be the same.
-- Disable split bars for both hosts.
-- Set crosslink control override as DSD/USP on one host, USD/DSP on
+Intel Non-transparent Bridge (NTB) needs special BIOS settings on both systems.
+Note that for 4th Generation Intel® Xeon® Scalable Processors, option ``Port
+Subsystem Mode`` should be changed from ``Gen5`` to ``Gen4 Only``, then reboot.
+
+- Set ``Non-Transparent Bridge PCIe Port Definition`` for needed PCIe ports as
+ ``NTB to NTB`` mode, on both hosts.
+- Set ``Enable NTB BARs`` as ``Enabled``, on both hosts.
+- Set ``Enable SPLIT BARs`` as ``Disabled``, on both hosts.
+- Set ``Imbar1 Size``, ``Imbar2 Size``, ``Embar1 Size`` and ``Embar2 Size``, as
+ 12-29 (i.e., 4K-512M) for 2nd Generation Intel® Xeon® Scalable Processors; as
+ 12-51 (i.e., 4K-128PB) for 3rd and 4th Generation Intel® Xeon® Scalable
+ Processors. Note that those bar sizes on both hosts should be the same.
+- Set ``Crosslink Control override`` as ``DSD/USP`` on one host, ``USD/DSP`` on
another host.
-- Disable PCIe PII SSC (Spread Spectrum Clocking) for both hosts. This
- is a hardware requirement.
+- Set ``PCIe PLL SSC (Spread Spectrum Clocking)`` as ``Disabled``, on both
+ hosts. This is a hardware requirement when using Re-timer Cards.
Device Setup
@@ -145,4 +149,8 @@ like the following:
Limitation
----------
-- This PMD only supports Intel Skylake and Ice Lake platforms.
+This PMD is only supported on Intel Xeon Platforms:
+
+- 4th Generation Intel® Xeon® Scalable Processors.
+- 3rd Generation Intel® Xeon® Scalable Processors.
+- 2nd Generation Intel® Xeon® Scalable Processors.
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH] doc: update BIOS setting and supported HW list for NTB
2023-07-03 9:24 [PATCH] doc: update BIOS setting and supported HW list for NTB Junfeng Guo
@ 2023-07-03 9:35 ` Wu, Jingjing
2023-07-06 20:29 ` Stephen Hemminger
2023-07-20 4:00 ` Thomas Monjalon
0 siblings, 2 replies; 6+ messages in thread
From: Wu, Jingjing @ 2023-07-03 9:35 UTC (permalink / raw)
To: Guo, Junfeng; +Cc: dev, stable
> -----Original Message-----
> From: Guo, Junfeng <junfeng.guo@intel.com>
> Sent: Monday, July 3, 2023 5:25 PM
> To: Wu, Jingjing <jingjing.wu@intel.com>
> Cc: dev@dpdk.org; stable@dpdk.org; Guo, Junfeng <junfeng.guo@intel.com>
> Subject: [PATCH] doc: update BIOS setting and supported HW list for NTB
>
> Update BIOS settings and supported platform list for Intel NTB.
>
> Fixes: f5057be340e4 ("raw/ntb: support Intel Ice Lake")
> Cc: stable@dpdk.org
>
> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] doc: update BIOS setting and supported HW list for NTB
2023-07-03 9:35 ` Wu, Jingjing
@ 2023-07-06 20:29 ` Stephen Hemminger
2023-07-07 8:47 ` Guo, Junfeng
2023-07-20 4:00 ` Thomas Monjalon
1 sibling, 1 reply; 6+ messages in thread
From: Stephen Hemminger @ 2023-07-06 20:29 UTC (permalink / raw)
To: Wu, Jingjing; +Cc: Guo, Junfeng, dev, stable
On Mon, 3 Jul 2023 09:35:29 +0000
"Wu, Jingjing" <jingjing.wu@intel.com> wrote:
> > -----Original Message-----
> > From: Guo, Junfeng <junfeng.guo@intel.com>
> > Sent: Monday, July 3, 2023 5:25 PM
> > To: Wu, Jingjing <jingjing.wu@intel.com>
> > Cc: dev@dpdk.org; stable@dpdk.org; Guo, Junfeng <junfeng.guo@intel.com>
> > Subject: [PATCH] doc: update BIOS setting and supported HW list for NTB
> >
> > Update BIOS settings and supported platform list for Intel NTB.
> >
> > Fixes: f5057be340e4 ("raw/ntb: support Intel Ice Lake")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
>
> Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Kind of unfortunate that the documentation does not list why non-standard
settings are needed for DPDK.
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH] doc: update BIOS setting and supported HW list for NTB
2023-07-06 20:29 ` Stephen Hemminger
@ 2023-07-07 8:47 ` Guo, Junfeng
0 siblings, 0 replies; 6+ messages in thread
From: Guo, Junfeng @ 2023-07-07 8:47 UTC (permalink / raw)
To: Stephen Hemminger, Wu, Jingjing; +Cc: dev, stable
> -----Original Message-----
> From: Stephen Hemminger <stephen@networkplumber.org>
> Sent: Friday, July 7, 2023 04:30
> To: Wu, Jingjing <jingjing.wu@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org;
> stable@dpdk.org
> Subject: Re: [PATCH] doc: update BIOS setting and supported HW list for
> NTB
>
> On Mon, 3 Jul 2023 09:35:29 +0000
> "Wu, Jingjing" <jingjing.wu@intel.com> wrote:
>
> > > -----Original Message-----
> > > From: Guo, Junfeng <junfeng.guo@intel.com>
> > > Sent: Monday, July 3, 2023 5:25 PM
> > > To: Wu, Jingjing <jingjing.wu@intel.com>
> > > Cc: dev@dpdk.org; stable@dpdk.org; Guo, Junfeng
> <junfeng.guo@intel.com>
> > > Subject: [PATCH] doc: update BIOS setting and supported HW list for
> NTB
> > >
> > > Update BIOS settings and supported platform list for Intel NTB.
> > >
> > > Fixes: f5057be340e4 ("raw/ntb: support Intel Ice Lake")
> > > Cc: stable@dpdk.org
> > >
> > > Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
> >
> > Acked-by: Jingjing Wu <jingjing.wu@intel.com>
>
> Kind of unfortunate that the documentation does not list why non-
> standard
> settings are needed for DPDK.
Thanks for the comments!
Yes, these BIOS settings are used to enable the NTB device so that it can
be used by DPDK PMD or other drivers.
I'm not quite sure about the principle of each required item. But without
them, the NTB device cannot show up in the PCI buses list.
We can update them gradually once we know the purpose of each setting.
Thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] doc: update BIOS setting and supported HW list for NTB
2023-07-03 9:35 ` Wu, Jingjing
2023-07-06 20:29 ` Stephen Hemminger
@ 2023-07-20 4:00 ` Thomas Monjalon
1 sibling, 0 replies; 6+ messages in thread
From: Thomas Monjalon @ 2023-07-20 4:00 UTC (permalink / raw)
To: Guo, Junfeng; +Cc: stable, dev, Wu, Jingjing
> > Update BIOS settings and supported platform list for Intel NTB.
> >
> > Fixes: f5057be340e4 ("raw/ntb: support Intel Ice Lake")
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
>
> Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Applied and replaced unicode characters with "\ |reg|" syntax.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] doc: update BIOS setting and supported HW list for NTB
@ 2023-07-03 9:11 Junfeng Guo
0 siblings, 0 replies; 6+ messages in thread
From: Junfeng Guo @ 2023-07-03 9:11 UTC (permalink / raw)
To: jingjing.wu, helin.zhang; +Cc: Junfeng Guo, stable
Update BIOS settings and supported platform list for Intel NTB.
Fixes: f5057be340e4 ("raw/ntb: support Intel Ice Lake")
Cc: stable@dpdk.org
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
---
doc/guides/rawdevs/ntb.rst | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/doc/guides/rawdevs/ntb.rst b/doc/guides/rawdevs/ntb.rst
index 2bb115d13f..c34512177a 100644
--- a/doc/guides/rawdevs/ntb.rst
+++ b/doc/guides/rawdevs/ntb.rst
@@ -17,18 +17,22 @@ some information by using scratchpad registers.
BIOS setting on Intel Xeon
--------------------------
-Intel Non-transparent Bridge needs special BIOS setting. The reference for
-Skylake is https://www.intel.com/content/dam/support/us/en/documents/server-products/Intel_Xeon_Processor_Scalable_Family_BIOS_User_Guide.pdf
-
-- Set the needed PCIe port as NTB to NTB mode on both hosts.
-- Enable NTB bars and set bar size of bar 23 and bar 45 as 12-29 (4K-512M)
- on both hosts (for Ice Lake, bar size can be set as 12-51, namely 4K-128PB).
- Note that bar size on both hosts should be the same.
-- Disable split bars for both hosts.
-- Set crosslink control override as DSD/USP on one host, USD/DSP on
+Intel Non-transparent Bridge (NTB) needs special BIOS settings on both systems.
+Note that for 4th Generation Intel® Xeon® Scalable Processors, option ``Port
+Subsystem Mode`` should be changed from ``Gen5`` to ``Gen4 Only``, then reboot.
+
+- Set ``Non-Transparent Bridge PCIe Port Definition`` for needed PCIe ports as
+ ``NTB to NTB`` mode, on both hosts.
+- Set ``Enable NTB BARs`` as ``Enabled``, on both hosts.
+- Set ``Enable SPLIT BARs`` as ``Disabled``, on both hosts.
+- Set ``Imbar1 Size``, ``Imbar2 Size``, ``Embar1 Size`` and ``Embar2 Size``, as
+ 12-29 (i.e., 4K-512M) for 2nd Generation Intel® Xeon® Scalable Processors; as
+ 12-51 (i.e., 4K-128PB) for 3rd and 4th Generation Intel® Xeon® Scalable
+ Processors. Note that those bar sizes on both hosts should be the same.
+- Set ``Crosslink Control override`` as ``DSD/USP`` on one host, ``USD/DSP`` on
another host.
-- Disable PCIe PII SSC (Spread Spectrum Clocking) for both hosts. This
- is a hardware requirement.
+- Set ``PCIe PLL SSC (Spread Spectrum Clocking)`` as ``Disabled``, on both
+ hosts. This is a hardware requirement when using Re-timer Cards.
Device Setup
@@ -145,4 +149,8 @@ like the following:
Limitation
----------
-- This PMD only supports Intel Skylake and Ice Lake platforms.
+This PMD is only supported on Intel Xeon Platforms:
+
+- 4th Generation Intel® Xeon® Scalable Processors.
+- 3rd Generation Intel® Xeon® Scalable Processors.
+- 2nd Generation Intel® Xeon® Scalable Processors.
--
2.34.1
^ permalink raw reply [flat|nested] 6+ messages in thread
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2023-07-03 9:24 [PATCH] doc: update BIOS setting and supported HW list for NTB Junfeng Guo
2023-07-03 9:35 ` Wu, Jingjing
2023-07-06 20:29 ` Stephen Hemminger
2023-07-07 8:47 ` Guo, Junfeng
2023-07-20 4:00 ` Thomas Monjalon
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2023-07-03 9:11 Junfeng Guo
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