From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 80DE242EDB for ; Fri, 21 Jul 2023 16:56:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5C46240E2D; Fri, 21 Jul 2023 16:56:59 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2060.outbound.protection.outlook.com [40.107.220.60]) by mails.dpdk.org (Postfix) with ESMTP id D2DB940DDC for ; Fri, 21 Jul 2023 16:56:57 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SDQ442sVLqKHsu3bBO4thCCin94lSunZiEGiwnC1F9usq/70wLouzRFZuVwD71+SaHMQ+D438/8VwDHgGgNAFFRmF6xby4F/OwTtAwXlXItf3RVQCUiAWLh0nLP5fhN+DAxs3DcBQaLE0UHwv2dkxh+5VUgDE1+4oI/lxOaMq9Hagjco8wr9L7FoW4uVACAF+9Fd6MLJwx+1e+r/ZutDCSV8lmRDzYjSl4HKVgXI5RXWSkSO6vioGZU4njndTtVqobRJPNSfM3UwGLmiB1v72eyWJtQ1F8OIUeXn0uyaRWk0aLkx8AXsVh268co9oIJKrbUk764OUkRdXFU8wwkUFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mkMPD2yIzta31NOo2FIUPLqEy2fSeLHn6uEH8pP5Y5Y=; b=HbrywuZnoVN4ZvAm11LE966pxoa94XmK33jNOY8Ljpt1NSynG3J9JBjTpA81xp9LPzGUbLnVUnLgXnmH8KeIZM84HMYZ7r2QAJjPSUOZ9UtqLey5FdtiStalr80Jq9e0HiR4JjQapmSdtuQl6KADLjOirEFWyyzGrpCCE7h2jN1i2e7E/2047mT7SJMU2MOISNsOmggPWEnAXpOaRH06qAVQa7/MJeH4+dSjG/3/C0ghrApvX1Aj/P/T+sU0uHVHedY/WHeAp43fgj/Rmnq+dZLvPSHtpUMWTEDmcPRfTeyClYacSdqU+z889nQ7BleO2O8QOZGcAF0ZcColPqF6OA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mkMPD2yIzta31NOo2FIUPLqEy2fSeLHn6uEH8pP5Y5Y=; b=FzMkc8/wC8VgF9onO5hYeGh2SAMbRykPmuPNFyLXYt16ZIXam6zGInRM4LQvqhv5TsShPFlLry7zoQhWV8KWfFnvoWM1kHj/GFDAbRbddwAxJfzyfSqW5zkmfuK6mJSnOlEWsocz2SDz16bxkipmb//Uxn0SjCDxi2htg+kLfdg4MBI580Q8qfXIpT/+/9z80tlVPlfTyRvT74pLbrSeKb5f/kCYgomGczhwVrDA+KjNYzhWIvVqT9+LdiS1vd1Q9t4c/jrBqnLVve6eUCX5ABysjkO4SOFQ+3vsgaKrlkii+jGScrMl5G/B+eunQDgJbstJp6gJiFrC5m1oLKof3w== Received: from SJ0PR03CA0050.namprd03.prod.outlook.com (2603:10b6:a03:33e::25) by CY8PR12MB8338.namprd12.prod.outlook.com (2603:10b6:930:7b::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.25; Fri, 21 Jul 2023 14:56:56 +0000 Received: from DM6NAM11FT034.eop-nam11.prod.protection.outlook.com (2603:10b6:a03:33e:cafe::85) by SJ0PR03CA0050.outlook.office365.com (2603:10b6:a03:33e::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.25 via Frontend Transport; Fri, 21 Jul 2023 14:56:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT034.mail.protection.outlook.com (10.13.173.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.28 via Frontend Transport; Fri, 21 Jul 2023 14:56:55 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Fri, 21 Jul 2023 07:56:41 -0700 Received: from pegasus01.mtr.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Fri, 21 Jul 2023 07:56:39 -0700 From: Alexander Kozyrev To: CC: , , Subject: [PATCH 21.11] net/mlx5: fix MPRQ stride size to accommodate the headroom Date: Fri, 21 Jul 2023 17:56:26 +0300 Message-ID: <20230721145626.40942-1-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT034:EE_|CY8PR12MB8338:EE_ X-MS-Office365-Filtering-Correlation-Id: 08c35406-4e5b-4557-583a-08db89fab9d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DemPXl0CvTOJGPrPmW2z6/06fA3NFIZf+b1efdXuEXiB+Zt9qRrYYkRJE2vknBJrM3J8xPPYz76rYqENrFYSUtHYvQs0l4kTDU/eCyyi3tsRXYTgyXxMaQ1cU6vNQ398jNS3cUpqzwO0daLn/vUmc5bAxMe8LwwG45+tXtXBN52Ymf9h0VjyMd1yE0ENr+UdBBxoGiiemK4PeYwkrn5bI0hIAOROrZg1qLPLWdKuSeRybnE/vrTqa5+RcJnZklbAvEKut0PE9ZE71d840M4DU5RYy9r24YEaYAB0r8bt4aFtgq3+a50O3WRl42IyJjpxNOkY1gDRXeZCMKQpQqHga3B94UqJR4sHRQ6f2Mgt4NtCXHSVhRcvOk1EFGgPwK+XFU+aAdTN6tswwPOPWbpiqaMjhxgNM+PPGuARAYxd7F/leoUOm+1nleLT3LMCG9cTnH9OSF6Gf/jgYHJ0y3OxlGIWmsR/wSOJq0qbQx9wPu6mj9z97TxGmEMJ5QgMnfTIQ594kWn00jasjhoU/2uVOzeotGulrVOFU3pImZq9N9PgT9F3sC6Er7YzApFRtrHX0ZN1yJUYRLznUoLOX4p+Dcn1mkUTYrpuDj9DFM4HJfea6GosxeEYffJ4jOMjpYdZ+mX7FqoXNxLuYKNrSShML+h2uiZnaWv9RBirkBCRKYOVbGivvPiECcSlDbDQMlsAhAUIMvdHSO6NOoE9DTP1QwoieTr+jJDrX4b2zuPcF5pWzTuTHtiobNv5GtHAm5Cv X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(346002)(136003)(396003)(376002)(39860400002)(82310400008)(451199021)(36840700001)(40470700004)(46966006)(40460700003)(83380400001)(2906002)(426003)(36756003)(47076005)(2616005)(36860700001)(8676002)(8936002)(478600001)(70586007)(70206006)(41300700001)(54906003)(316002)(6916009)(4326008)(5660300002)(16526019)(336012)(186003)(1076003)(26005)(6666004)(40480700001)(86362001)(7636003)(356005)(82740400003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2023 14:56:55.4050 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08c35406-4e5b-4557-583a-08db89fab9d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8338 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit e6479f009fbd9c8e873807cc928dcf91a151aba9 ] The space for the headroom is reserved at the end of every MPRQ stride for the next packet. The Rx burst logic is to copy any overlapping packet data if there is an overlap with this reserved headroom space. But it is not possible if the headroom size is bigger than the whole stride. Adjust the stride size to make sure the stride size is greater than the headroom size. Fixes: 34776af600 ("net/mlx5: fix MPRQ stride devargs adjustment") Signed-off-by: Alexander Kozyrev Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_os.c | 1 + drivers/net/mlx5/mlx5_rxq.c | 41 ++++++++++++++++++++++---------- 2 files changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index e79b1a275c..ab69ee21ad 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1202,6 +1202,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, config->mprq.log_min_stride_wqe_size = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; + config->mprq.log_stride_size = MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE; if (config->devx) { config->mprq.log_min_stride_wqe_size = config->hca_attr.log_min_stride_wqe_sz; diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 47db585042..4a8fc8721d 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -1446,23 +1446,38 @@ mlx5_mprq_prepare(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, } else { *actual_log_stride_num = config->mprq.log_stride_num; } - if (config->mprq.log_stride_size) { - /* Checks if chosen size of stride is in supported range. */ - if (config->mprq.log_stride_size > log_max_stride_size || - config->mprq.log_stride_size < log_min_stride_size) { - *actual_log_stride_size = log_def_stride_size; + /* Checks if chosen size of stride is in supported range. */ + if (config->mprq.log_stride_size > log_max_stride_size || + config->mprq.log_stride_size < log_min_stride_size) { + *actual_log_stride_size = log_def_stride_size; + DRV_LOG(WARNING, + "Port %u Rx queue %u size of a stride for Multi-Packet RQ is out of range, setting default value (%u)", + dev->data->port_id, idx, + RTE_BIT32(log_def_stride_size)); + } else { + *actual_log_stride_size = config->mprq.log_stride_size; + } + /* Make the stride fit the mbuf size by default. */ + if (*actual_log_stride_size == MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE) { + if (min_mbuf_size <= RTE_BIT32(log_max_stride_size)) { DRV_LOG(WARNING, - "Port %u Rx queue %u size of a stride for Multi-Packet RQ is out of range, setting default value (%u)", - dev->data->port_id, idx, - RTE_BIT32(log_def_stride_size)); + "Port %u Rx queue %u size of a stride for Multi-Packet RQ is adjusted to match the mbuf size (%u)", + dev->data->port_id, idx, min_mbuf_size); + *actual_log_stride_size = log2above(min_mbuf_size); } else { - *actual_log_stride_size = config->mprq.log_stride_size; + goto unsupport; } - } else { - if (min_mbuf_size <= RTE_BIT32(log_max_stride_size)) - *actual_log_stride_size = log2above(min_mbuf_size); - else + } + /* Make sure the stride size is greater than the headroom. */ + if (RTE_BIT32(*actual_log_stride_size) < RTE_PKTMBUF_HEADROOM) { + if (RTE_BIT32(log_max_stride_size) > RTE_PKTMBUF_HEADROOM) { + DRV_LOG(WARNING, + "Port %u Rx queue %u size of a stride for Multi-Packet RQ is adjusted to accommodate the headroom (%u)", + dev->data->port_id, idx, RTE_PKTMBUF_HEADROOM); + *actual_log_stride_size = log2above(RTE_PKTMBUF_HEADROOM); + } else { goto unsupport; + } } log_stride_wqe_size = *actual_log_stride_num + *actual_log_stride_size; /* Check if WQE buffer size is supported by hardware. */ -- 2.18.2