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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SA2PEPF000015C9.mail.protection.outlook.com (10.167.241.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6652.20 via Frontend Transport; Wed, 9 Aug 2023 23:52:02 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Wed, 9 Aug 2023 16:51:46 -0700 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 9 Aug 2023 16:51:44 -0700 From: Xueming Li To: Jiawen Wu CC: dpdk stable Subject: patch 'net/txgbe: adapt to MNG veto bit setting' has been queued to stable release 22.11.3 Date: Thu, 10 Aug 2023 07:47:46 +0800 Message-ID: <20230809234930.32424-25-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230809234930.32424-1-xuemingl@nvidia.com> References: <20230625063544.11183-1-xuemingl@nvidia.com> <20230809234930.32424-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C9:EE_|MW4PR12MB7119:EE_ X-MS-Office365-Filtering-Correlation-Id: e43e7ca6-049c-4ecf-27de-08db9933a0eb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Aug 2023 23:52:02.3798 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e43e7ca6-049c-4ecf-27de-08db9933a0eb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7119 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.3 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 08/11/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=57b3a57dfa1ee05e8738f475bf3722e738f96fe3 Thanks. Xueming Li --- >From 57b3a57dfa1ee05e8738f475bf3722e738f96fe3 Mon Sep 17 00:00:00 2001 From: Jiawen Wu Date: Wed, 14 Jun 2023 10:34:23 +0800 Subject: [PATCH] net/txgbe: adapt to MNG veto bit setting Cc: Xueming Li [ upstream commit 12011b11a3d6339082e647082d30f97f49f6a468 ] In the new firmware, MNG veto bit is set by default for new features. It leads to several issues, so driver makes the following changes: 1. Change the way by sending reset command to firmware to LAN reset. So that MNG domain will not be reset. 2. Change the hardware flush register since the original register cannot be read temporarily after LAN reset. 3. Remove checking of MNG veto bit when handling Tx laser. 4. Workaround for GPIO interrupt lost. Fixes: f58ae2fcfea6 ("net/txgbe: add HW init and reset operation") Fixes: e4c515a7bc7e ("net/txgbe: add multi-speed link setup") Fixes: d3bb4a04eac1 ("net/txgbe: add SFP hotplug identification") Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/txgbe_hw.c | 23 +++-------------------- drivers/net/txgbe/base/txgbe_regs.h | 15 ++++++++++++++- drivers/net/txgbe/txgbe_ethdev.c | 27 +++++++++++++++++++++++++++ 3 files changed, 44 insertions(+), 21 deletions(-) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index 8966453a03..601c30ab81 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -2987,10 +2987,6 @@ void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw) { u32 esdp_reg = rd32(hw, TXGBE_GPIODATA); - /* Blocked by MNG FW so bail */ - if (txgbe_check_reset_blocked(hw)) - return; - if (txgbe_close_notify(hw)) txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_LEDCTL_10G | TXGBE_LEDCTL_1G | TXGBE_LEDCTL_ACTIVE); @@ -3038,10 +3034,6 @@ void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw) **/ void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw) { - /* Blocked by MNG FW so bail */ - if (txgbe_check_reset_blocked(hw)) - return; - if (hw->mac.autotry_restart) { txgbe_disable_tx_laser_multispeed_fiber(hw); txgbe_enable_tx_laser_multispeed_fiber(hw); @@ -3432,18 +3424,9 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw) autoc = hw->mac.autoc_read(hw); mac_reset_top: - /* - * Issue global reset to the MAC. Needs to be SW reset if link is up. - * If link reset is used when link is up, it might reset the PHY when - * mng is using it. If link is down or the flag to force full link - * reset is set, then perform link reset. - */ - if (txgbe_mng_present(hw)) { - txgbe_hic_reset(hw); - } else { - wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id)); - txgbe_flush(hw); - } + /* Do LAN reset, the MNG domain will not be reset. */ + wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id)); + txgbe_flush(hw); usec_delay(10); txgbe_reset_misc(hw); diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 911bb6e04e..79290a7afe 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1579,6 +1579,7 @@ enum txgbe_5tuple_protocol { #define TXGBE_GPIOINTMASK 0x014834 #define TXGBE_GPIOINTTYPE 0x014838 #define TXGBE_GPIOINTSTAT 0x014840 +#define TXGBE_GPIORAWINTSTAT 0x014844 #define TXGBE_GPIOEOI 0x01484C @@ -1884,7 +1885,19 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, } /* flush all write operations */ -#define txgbe_flush(hw) rd32(hw, 0x00100C) +static inline void txgbe_flush(struct txgbe_hw *hw) +{ + switch (hw->mac.type) { + case txgbe_mac_raptor: + rd32(hw, TXGBE_PWR); + break; + case txgbe_mac_raptor_vf: + rd32(hw, TXGBE_VFSTATUS); + break; + default: + break; + } +} #define rd32a(hw, reg, idx) ( \ rd32((hw), (reg) + ((idx) << 2))) diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 6562bddd6b..9fb30c896a 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -1530,6 +1530,25 @@ txgbe_dev_configure(struct rte_eth_dev *dev) return 0; } +static void txgbe_reinit_gpio_intr(struct txgbe_hw *hw) +{ + u32 reg; + + wr32(hw, TXGBE_GPIOINTMASK, 0xFF); + reg = rd32(hw, TXGBE_GPIORAWINTSTAT); + + if (reg & TXGBE_GPIOBIT_2) + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_2); + + if (reg & TXGBE_GPIOBIT_3) + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_3); + + if (reg & TXGBE_GPIOBIT_6) + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_6); + + wr32(hw, TXGBE_GPIOINTMASK, 0); +} + static void txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) { @@ -1668,6 +1687,10 @@ txgbe_dev_start(struct rte_eth_dev *dev) hw->mac.get_link_status = true; hw->dev_start = true; + /* workaround for GPIO intr lost when mng_veto bit is set */ + if (txgbe_check_reset_blocked(hw)) + txgbe_reinit_gpio_intr(hw); + /* configure PF module if SRIOV enabled */ txgbe_pf_host_configure(dev); @@ -1884,6 +1907,10 @@ txgbe_dev_stop(struct rte_eth_dev *dev) /* disable interrupts */ txgbe_disable_intr(hw); + /* workaround for GPIO intr lost when mng_veto bit is set */ + if (txgbe_check_reset_blocked(hw)) + txgbe_reinit_gpio_intr(hw); + /* reset the NIC */ txgbe_pf_reset_hw(hw); hw->adapter_stopped = 0; -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-08-09 21:51:18.890625300 +0800 +++ 0024-net-txgbe-adapt-to-MNG-veto-bit-setting.patch 2023-08-09 21:51:18.154352000 +0800 @@ -1 +1 @@ -From 12011b11a3d6339082e647082d30f97f49f6a468 Mon Sep 17 00:00:00 2001 +From 57b3a57dfa1ee05e8738f475bf3722e738f96fe3 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 12011b11a3d6339082e647082d30f97f49f6a468 ] @@ -18 +20,0 @@ -Cc: stable@dpdk.org @@ -23 +25 @@ - drivers/net/txgbe/base/txgbe_regs.h | 14 +++++++++++++- + drivers/net/txgbe/base/txgbe_regs.h | 15 ++++++++++++++- @@ -25 +27 @@ - 3 files changed, 43 insertions(+), 21 deletions(-) + 3 files changed, 44 insertions(+), 21 deletions(-) @@ -28 +30 @@ -index e7c9754d26..2952c408fd 100644 +index 8966453a03..601c30ab81 100644 @@ -31 +33 @@ -@@ -2988,10 +2988,6 @@ void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw) +@@ -2987,10 +2987,6 @@ void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw) @@ -42 +44 @@ -@@ -3039,10 +3035,6 @@ void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw) +@@ -3038,10 +3034,6 @@ void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw) @@ -53 +55 @@ -@@ -3433,18 +3425,9 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw) +@@ -3432,18 +3424,9 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw) @@ -76 +78 @@ -index bc2854b01a..79290a7afe 100644 +index 911bb6e04e..79290a7afe 100644 @@ -79 +81,9 @@ -@@ -1885,7 +1885,19 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, +@@ -1579,6 +1579,7 @@ enum txgbe_5tuple_protocol { + #define TXGBE_GPIOINTMASK 0x014834 + #define TXGBE_GPIOINTTYPE 0x014838 + #define TXGBE_GPIOINTSTAT 0x014840 ++#define TXGBE_GPIORAWINTSTAT 0x014844 + #define TXGBE_GPIOEOI 0x01484C + + +@@ -1884,7 +1885,19 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual, @@ -101 +111 @@ -index 5eff1a766e..36c74d353d 100644 +index 6562bddd6b..9fb30c896a 100644 @@ -104 +114 @@ -@@ -1531,6 +1531,25 @@ txgbe_dev_configure(struct rte_eth_dev *dev) +@@ -1530,6 +1530,25 @@ txgbe_dev_configure(struct rte_eth_dev *dev) @@ -130 +140 @@ -@@ -1680,6 +1699,10 @@ txgbe_dev_start(struct rte_eth_dev *dev) +@@ -1668,6 +1687,10 @@ txgbe_dev_start(struct rte_eth_dev *dev) @@ -141 +151 @@ -@@ -1897,6 +1920,10 @@ txgbe_dev_stop(struct rte_eth_dev *dev) +@@ -1884,6 +1907,10 @@ txgbe_dev_stop(struct rte_eth_dev *dev)