From: Hernan Vargas <hernan.vargas@intel.com>
To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,
maxime.coquelin@redhat.com
Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com,
Hernan Vargas <hernan.vargas@intel.com>,
stable@dpdk.org
Subject: [PATCH v1 1/1] baseband/acc: fix ACC100 HARQ input is alignment
Date: Tue, 19 Sep 2023 11:24:17 -0700 [thread overview]
Message-ID: <20230919182417.93374-2-hernan.vargas@intel.com> (raw)
In-Reply-To: <20230919182417.93374-1-hernan.vargas@intel.com>
Some constraints are imposed onto the ACC100 HARQ input size,
but that value is incorrectly aligned down when getting close to
max (Ncb-F) which is not required.
The wireless performance impact is negligeable but still causes a
few LLRs no to be combined at the very end of the circular buffer.
Fixes: 5802f36dd492 ("baseband/acc100: enforce additional check on FCW")
Cc: stable@dpdk.org
Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
---
drivers/baseband/acc/rte_acc100_pmd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/baseband/acc/rte_acc100_pmd.c b/drivers/baseband/acc/rte_acc100_pmd.c
index 5362d39c302f..c736f3e4201c 100644
--- a/drivers/baseband/acc/rte_acc100_pmd.c
+++ b/drivers/baseband/acc/rte_acc100_pmd.c
@@ -1218,7 +1218,7 @@ acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc_fcw_ld *fcw,
- op->ldpc_dec.n_filler);
/* Alignment on next 64B - Already enforced from HC output */
- harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC_HARQ_ALIGN_64B);
+ harq_in_length = RTE_ALIGN_CEIL(harq_in_length, ACC_HARQ_ALIGN_64B);
/* Stronger alignment requirement when in decompression mode */
if (fcw->hcin_decomp_mode > 0)
--
2.37.1
next parent reply other threads:[~2023-09-19 18:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230919182417.93374-1-hernan.vargas@intel.com>
2023-09-19 18:24 ` Hernan Vargas [this message]
2023-10-03 16:10 ` Maxime Coquelin
2023-10-12 12:53 ` Maxime Coquelin
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