From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 675834319F for ; Thu, 19 Oct 2023 01:59:59 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6094340A7A; Thu, 19 Oct 2023 01:59:59 +0200 (CEST) Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mails.dpdk.org (Postfix) with ESMTP id 900CC40291 for ; Thu, 19 Oct 2023 01:59:57 +0200 (CEST) Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-32da4ffd7e5so118834f8f.0 for ; Wed, 18 Oct 2023 16:59:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697673597; x=1698278397; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EpVviY8nqseF7UDFWBzxaI3HbUso+3h3SCjn6XLDMxg=; b=PW0A54JrCEdunYsV5oRvkhbsu1F3ZDLKmyBMwrPZQChe24gU+ZnJP6ygCORfNVhR5y 6N3q5gIVpSwkCrl1Q6QcGVS6blWydTTjQtrpkbV46KFHdGCzCKct0ebqGqIg6zXdbATH v0mHyVeHXSl7SSpb48eeE42YEultpx2TpTY7LdgtIT8aZlUVPqAqIf+4OPjnjM2AZ9s+ fB9KFfbQrCjaSEq35jv8UQB8vp1k2yKaLV+qsdYK+Bp4SmgaaQ0BNkFfAm4i5v2yVGul wekUCadqJosOfg6ZhXBECM+qYuilXeyGNNG3+zBIEt6k36Fy1Sv3Ij06vGCA7JyRrU2X 7RoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697673597; x=1698278397; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EpVviY8nqseF7UDFWBzxaI3HbUso+3h3SCjn6XLDMxg=; b=RpBiwkncrqRXhxFmr0DUQFXLE7Z9bSzDUniBf6KFxaqcEoEiaUzIxq91/0FVJfWr1v fEwBqgjoWaKIQyZBSRK18KUmfWiCcAT01Oaf1UYBijCYJLr5KOxI5HachCIjixVmjxhn EIXT3zrXeGGGD3hyIJMNA94GqzFGKjZCNpntM6uyu47YtFTFkjqqnnH9F6XFNXppzz9E hBf4M6qitHr+XxVzngX2meAM2wSzUjechBtGyu7tjjDh7LI/JYY66nDy/Yi/puoTuChS r7oWmcAwxwIYvJ9R4pbgeGol3l2ic6xt70ZULxMhPC4yTR2Oz3pSi6MoAntAq+GD0Oug lVhA== X-Gm-Message-State: AOJu0YzQOhmZp2tpOi4+Wr9wo00X+GibKUcp/ZP25TCTXVEOFQwizSmH EkmSUBM8y9HkiI4bupK5BQI+ZDcoZMYNug== X-Google-Smtp-Source: AGHT+IE3NYOfORu5NA6j7CE1F1CKhrZBcINwZnWU55hVSCZPb2m2JD3pOqUtk3G1nfjxAW383mG89g== X-Received: by 2002:a5d:4147:0:b0:329:6b62:8d18 with SMTP id c7-20020a5d4147000000b003296b628d18mr303244wrq.0.1697673597013; Wed, 18 Oct 2023 16:59:57 -0700 (PDT) Received: from localhost ([137.220.119.58]) by smtp.gmail.com with ESMTPSA id bs30-20020a056000071e00b0032d9a1f2ec3sm3222265wrb.27.2023.10.18.16.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 16:59:56 -0700 (PDT) From: luca.boccassi@gmail.com To: Huisong Li Cc: Dongdong Liu , dpdk stable Subject: patch 'net/hns3: fix order in NEON Rx' has been queued to stable release 20.11.10 Date: Thu, 19 Oct 2023 00:58:57 +0100 Message-Id: <20231018235930.3144-8-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231018235930.3144-1-luca.boccassi@gmail.com> References: <20231018235930.3144-1-luca.boccassi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 20.11.10 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 10/21/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/bluca/dpdk-stable This queued commit can be viewed at: https://github.com/bluca/dpdk-stable/commit/b88f88cdaa73e889e197a9257f86289bad2e6a05 Thanks. Luca Boccassi --- >From b88f88cdaa73e889e197a9257f86289bad2e6a05 Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Tue, 11 Jul 2023 18:24:45 +0800 Subject: [PATCH] net/hns3: fix order in NEON Rx [ upstream commit 7dd439ed998c36c8d0204c436cc656af08cfa5fc ] This patch reorders the order of the NEON Rx for better maintenance and easier understanding. Fixes: a3d4f4d291d7 ("net/hns3: support NEON Rx") Signed-off-by: Huisong Li Signed-off-by: Dongdong Liu --- drivers/net/hns3/hns3_rxtx_vec_neon.h | 80 +++++++++++---------------- 1 file changed, 32 insertions(+), 48 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx_vec_neon.h b/drivers/net/hns3/hns3_rxtx_vec_neon.h index 9c41c409de..e289fcc651 100644 --- a/drivers/net/hns3/hns3_rxtx_vec_neon.h +++ b/drivers/net/hns3/hns3_rxtx_vec_neon.h @@ -168,19 +168,12 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq, bd_vld = vset_lane_u16(rxdp[2].rx.bdtype_vld_udp0, bd_vld, 2); bd_vld = vset_lane_u16(rxdp[3].rx.bdtype_vld_udp0, bd_vld, 3); - /* load 2 mbuf pointer */ - mbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]); - bd_vld = vshl_n_u16(bd_vld, HNS3_UINT16_BIT - 1 - HNS3_RXD_VLD_B); bd_vld = vreinterpret_u16_s16( vshr_n_s16(vreinterpret_s16_u16(bd_vld), HNS3_UINT16_BIT - 1)); stat = ~vget_lane_u64(vreinterpret_u64_u16(bd_vld), 0); - - /* load 2 mbuf pointer again */ - mbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]); - if (likely(stat == 0)) bd_valid_num = HNS3_DEFAULT_DESCS_PER_LOOP; else @@ -188,20 +181,20 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq, if (bd_valid_num == 0) break; + /* load 4 mbuf pointer */ + mbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]); + mbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]); + + /* store 4 mbuf pointer into rx_pkts */ + vst1q_u64((uint64_t *)&rx_pkts[pos], mbp1); + vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2); + /* use offset to control below data load oper ordering */ offset = rxq->offset_table[bd_valid_num]; - /* store 2 mbuf pointer into rx_pkts */ - vst1q_u64((uint64_t *)&rx_pkts[pos], mbp1); - - /* read first two descs */ + /* read 4 descs */ descs[0] = vld2q_u64((uint64_t *)(rxdp + offset)); descs[1] = vld2q_u64((uint64_t *)(rxdp + offset + 1)); - - /* store 2 mbuf pointer into rx_pkts again */ - vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2); - - /* read remains two descs */ descs[2] = vld2q_u64((uint64_t *)(rxdp + offset + 2)); descs[3] = vld2q_u64((uint64_t *)(rxdp + offset + 3)); @@ -209,56 +202,47 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq, pkt_mbuf1.val[1] = vreinterpretq_u8_u64(descs[0].val[1]); pkt_mbuf2.val[0] = vreinterpretq_u8_u64(descs[1].val[0]); pkt_mbuf2.val[1] = vreinterpretq_u8_u64(descs[1].val[1]); - - /* pkt 1,2 convert format from desc to pktmbuf */ - pkt_mb1 = vqtbl2q_u8(pkt_mbuf1, shuf_desc_fields_msk); - pkt_mb2 = vqtbl2q_u8(pkt_mbuf2, shuf_desc_fields_msk); - - /* store the first 8 bytes of pkt 1,2 mbuf's rearm_data */ - *(uint64_t *)&sw_ring[pos + 0].mbuf->rearm_data = - rxq->mbuf_initializer; - *(uint64_t *)&sw_ring[pos + 1].mbuf->rearm_data = - rxq->mbuf_initializer; - - /* pkt 1,2 remove crc */ - tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust); - pkt_mb1 = vreinterpretq_u8_u16(tmp); - tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust); - pkt_mb2 = vreinterpretq_u8_u16(tmp); - pkt_mbuf3.val[0] = vreinterpretq_u8_u64(descs[2].val[0]); pkt_mbuf3.val[1] = vreinterpretq_u8_u64(descs[2].val[1]); pkt_mbuf4.val[0] = vreinterpretq_u8_u64(descs[3].val[0]); pkt_mbuf4.val[1] = vreinterpretq_u8_u64(descs[3].val[1]); - /* pkt 3,4 convert format from desc to pktmbuf */ + /* 4 packets convert format from desc to pktmbuf */ + pkt_mb1 = vqtbl2q_u8(pkt_mbuf1, shuf_desc_fields_msk); + pkt_mb2 = vqtbl2q_u8(pkt_mbuf2, shuf_desc_fields_msk); pkt_mb3 = vqtbl2q_u8(pkt_mbuf3, shuf_desc_fields_msk); pkt_mb4 = vqtbl2q_u8(pkt_mbuf4, shuf_desc_fields_msk); - /* pkt 1,2 save to rx_pkts mbuf */ - vst1q_u8((void *)&sw_ring[pos + 0].mbuf->rx_descriptor_fields1, - pkt_mb1); - vst1q_u8((void *)&sw_ring[pos + 1].mbuf->rx_descriptor_fields1, - pkt_mb2); - - /* pkt 3,4 remove crc */ + /* 4 packets remove crc */ + tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust); + pkt_mb1 = vreinterpretq_u8_u16(tmp); + tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust); + pkt_mb2 = vreinterpretq_u8_u16(tmp); tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust); pkt_mb3 = vreinterpretq_u8_u16(tmp); tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust); pkt_mb4 = vreinterpretq_u8_u16(tmp); - /* store the first 8 bytes of pkt 3,4 mbuf's rearm_data */ - *(uint64_t *)&sw_ring[pos + 2].mbuf->rearm_data = - rxq->mbuf_initializer; - *(uint64_t *)&sw_ring[pos + 3].mbuf->rearm_data = - rxq->mbuf_initializer; - - /* pkt 3,4 save to rx_pkts mbuf */ + /* save packet info to rx_pkts mbuf */ + vst1q_u8((void *)&sw_ring[pos + 0].mbuf->rx_descriptor_fields1, + pkt_mb1); + vst1q_u8((void *)&sw_ring[pos + 1].mbuf->rx_descriptor_fields1, + pkt_mb2); vst1q_u8((void *)&sw_ring[pos + 2].mbuf->rx_descriptor_fields1, pkt_mb3); vst1q_u8((void *)&sw_ring[pos + 3].mbuf->rx_descriptor_fields1, pkt_mb4); + /* store the first 8 bytes of packets mbuf's rearm_data */ + *(uint64_t *)&sw_ring[pos + 0].mbuf->rearm_data = + rxq->mbuf_initializer; + *(uint64_t *)&sw_ring[pos + 1].mbuf->rearm_data = + rxq->mbuf_initializer; + *(uint64_t *)&sw_ring[pos + 2].mbuf->rearm_data = + rxq->mbuf_initializer; + *(uint64_t *)&sw_ring[pos + 3].mbuf->rearm_data = + rxq->mbuf_initializer; + rte_prefetch_non_temporal(rxdp + HNS3_DEFAULT_DESCS_PER_LOOP); parse_retcode = hns3_desc_parse_field(rxq, &sw_ring[pos], -- 2.39.2 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-10-19 00:28:56.655193583 +0100 +++ 0008-net-hns3-fix-order-in-NEON-Rx.patch 2023-10-19 00:28:56.201804098 +0100 @@ -1 +1 @@ -From 7dd439ed998c36c8d0204c436cc656af08cfa5fc Mon Sep 17 00:00:00 2001 +From b88f88cdaa73e889e197a9257f86289bad2e6a05 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 7dd439ed998c36c8d0204c436cc656af08cfa5fc ] + @@ -10 +11,0 @@ -Cc: stable@dpdk.org @@ -19 +20 @@ -index 564d831a48..0dc6b9f0a2 100644 +index 9c41c409de..e289fcc651 100644 @@ -22 +23 @@ -@@ -180,19 +180,12 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq, +@@ -168,19 +168,12 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq, @@ -42 +43 @@ -@@ -200,20 +193,20 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq, +@@ -188,20 +181,20 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq, @@ -72 +73 @@ -@@ -221,56 +214,47 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq, +@@ -209,56 +202,47 @@ hns3_recv_burst_vec(struct hns3_rx_queue *__restrict rxq,