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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2023 07:27:46.0514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e47249e6-8e10-4e9a-75f7-08dbebf5b066 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6131 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org AMD Epyc processors doesn't support get_tsc_freq_arch(). The patch allows graceful return to allow fallback to alternate TSC calibration. Fixes: 3dbc565e81a0 ("timer: honor arch-specific TSC frequency query") Cc: jerin.jacob@caviumnetworks.com Cc: stable@dpdk.org Signed-off-by: Sivaprasad Tummala --- lib/eal/x86/rte_cycles.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/lib/eal/x86/rte_cycles.c b/lib/eal/x86/rte_cycles.c index 69ed59b4f0..f147a5231d 100644 --- a/lib/eal/x86/rte_cycles.c +++ b/lib/eal/x86/rte_cycles.c @@ -10,6 +10,10 @@ #include #endif +#define x86_vendor_amd(t1, t2, t3) \ + ((t1 == 0x68747541) && /* htuA */ \ + (t2 == 0x444d4163) && /* DMAc */ \ + (t3 == 0x69746e65)) /* itne */ #include "eal_private.h" @@ -110,6 +114,18 @@ get_tsc_freq_arch(void) uint8_t mult, model; int32_t ret; +#ifdef RTE_TOOLCHAIN_MSVC + __cpuid(cpuinfo, 0); + a = cpuinfo[0]; + b = cpuinfo[1]; + c = cpuinfo[2]; + d = cpuinfo[3]; +#else + __cpuid(0, a, b, c, d); +#endif + if (x86_vendor_amd(b, c, d)) + return 0; + /* * Time Stamp Counter and Nominal Core Crystal Clock * Information Leaf -- 2.34.1