From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 91367433A3 for ; Thu, 23 Nov 2023 09:05:33 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 31877427E8; Thu, 23 Nov 2023 09:05:33 +0100 (CET) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 7E42342EFC for ; Thu, 23 Nov 2023 09:05:30 +0100 (CET) Received: from kwepemm000004.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4SbVv82DDczrVP9; Thu, 23 Nov 2023 16:01:56 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by kwepemm000004.china.huawei.com (7.193.23.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 23 Nov 2023 16:05:25 +0800 From: Huisong Li To: , CC: , Subject: [PATCH 21.11 3/4] net/hns3: fix LRO offload to report Date: Thu, 23 Nov 2023 16:05:28 +0800 Message-ID: <20231123080529.15216-4-lihuisong@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20231123080529.15216-1-lihuisong@huawei.com> References: <20231123080529.15216-1-lihuisong@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.69.192.56] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemm000004.china.huawei.com (7.193.23.18) X-CFilter-Loop: Reflected X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit a4b2c6815abd3e39daca2e2c93334b813e6a0be4 ] Some network engines, like part of HIP09, may not support LRO offload, but this offload capability is also reported to user. So this patch determines whether driver reports this capability based on the capabilities from firmware. In addition, some network engines, like HIP08, always support LRO offload and their firmware don't report this capability. So this patch has to move getting revision ID codes to earlier stage and set default capabilities for these network engines based on revision ID. Fixes: ab2e2e344163 ("net/hns3: get device capability in primary process") Fixes: f5ed7d99cf45 ("net/hns3: extract common function to obtain revision ID") Signed-off-by: Huisong Li Signed-off-by: Jie Hai --- drivers/net/hns3/hns3_cmd.c | 17 ++++++++++++++++- drivers/net/hns3/hns3_cmd.h | 1 + drivers/net/hns3/hns3_common.c | 5 +++-- drivers/net/hns3/hns3_ethdev.c | 8 ++++---- drivers/net/hns3/hns3_ethdev.h | 1 + drivers/net/hns3/hns3_ethdev_vf.c | 8 ++++---- drivers/net/hns3/hns3_rxtx.c | 3 +++ 7 files changed, 32 insertions(+), 11 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index 13f7e37511..9b721ccc25 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -511,6 +511,8 @@ hns3_parse_capability(struct hns3_hw *hw, hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RAS_IMP_B, 1); if (hns3_get_bit(caps, HNS3_CAPS_TM_B)) hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TM_B, 1); + if (hns3_get_bit(caps, HNS3_CAPS_GRO_B)) + hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_GRO_B, 1); } static uint32_t @@ -545,6 +547,19 @@ hns3_set_dcb_capability(struct hns3_hw *hw) hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); } +static void +hns3_set_default_capability(struct hns3_hw *hw) +{ + hns3_set_dcb_capability(hw); + + /* + * The firmware of the network engines with HIP08 do not report some + * capabilities, like GRO. Set default capabilities for it. + */ + if (hw->revision < PCI_REVISION_ID_HIP09_A) + hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_GRO_B, 1); +} + static int hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw) { @@ -563,7 +578,7 @@ hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw) hw->fw_version = rte_le_to_cpu_32(resp->firmware); - hns3_set_dcb_capability(hw); + hns3_set_default_capability(hw); /* * Make sure mask the capability before parse capability because it diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 79b9023602..e1fab05489 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -319,6 +319,7 @@ enum HNS3_CAPS_BITS { HNS3_CAPS_RAS_IMP_B, HNS3_CAPS_RXD_ADV_LAYOUT_B = 15, HNS3_CAPS_TM_B = 19, + HNS3_CAPS_GRO_B = 20, }; /* Capabilities of VF dependent on the PF */ diff --git a/drivers/net/hns3/hns3_common.c b/drivers/net/hns3/hns3_common.c index 8641b90f67..ace5be01d5 100644 --- a/drivers/net/hns3/hns3_common.c +++ b/drivers/net/hns3/hns3_common.c @@ -70,8 +70,7 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) RTE_ETH_RX_OFFLOAD_SCATTER | RTE_ETH_RX_OFFLOAD_VLAN_STRIP | RTE_ETH_RX_OFFLOAD_VLAN_FILTER | - RTE_ETH_RX_OFFLOAD_RSS_HASH | - RTE_ETH_RX_OFFLOAD_TCP_LRO); + RTE_ETH_RX_OFFLOAD_RSS_HASH); info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | RTE_ETH_TX_OFFLOAD_TCP_CKSUM | @@ -99,6 +98,8 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info) if (hns3_dev_get_support(hw, PTP)) info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP; + if (hns3_dev_get_support(hw, GRO)) + info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TCP_LRO; info->rx_desc_lim = (struct rte_eth_desc_lim) { .nb_max = HNS3_MAX_RING_DESC, diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index bf612b1830..d71f032bda 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2692,10 +2692,6 @@ hns3_get_capability(struct hns3_hw *hw) struct hns3_pf *pf = &hns->pf; int ret; - ret = hns3_get_pci_revision_id(hw, &hw->revision); - if (ret) - return ret; - ret = hns3_query_mac_stats_reg_num(hw); if (ret) return ret; @@ -4560,6 +4556,10 @@ hns3_init_pf(struct rte_eth_dev *eth_dev) /* Get hardware io base address from pcie BAR2 IO space */ hw->io_base = pci_dev->mem_resource[2].addr; + ret = hns3_get_pci_revision_id(hw, &hw->revision); + if (ret) + return ret; + /* Firmware command queue initialize */ ret = hns3_cmd_init_queue(hw); if (ret) { diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index 3496be6f73..1f435ea497 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -891,6 +891,7 @@ enum { HNS3_DEV_SUPPORT_RAS_IMP_B, HNS3_DEV_SUPPORT_TM_B, HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, + HNS3_DEV_SUPPORT_GRO_B, }; #define hns3_dev_get_support(hw, _name) \ diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index cea885d7d8..59e71c9614 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -761,10 +761,6 @@ hns3vf_get_capability(struct hns3_hw *hw) { int ret; - ret = hns3_get_pci_revision_id(hw, &hw->revision); - if (ret) - return ret; - if (hw->revision < PCI_REVISION_ID_HIP09_A) { hns3_set_default_dev_specifications(hw); hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE; @@ -1452,6 +1448,10 @@ hns3vf_init_vf(struct rte_eth_dev *eth_dev) /* Get hardware io base address from pcie BAR2 IO space */ hw->io_base = pci_dev->mem_resource[2].addr; + ret = hns3_get_pci_revision_id(hw, &hw->revision); + if (ret) + return ret; + /* Firmware command queue initialize */ ret = hns3_cmd_init_queue(hw); if (ret) { diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index a758300060..00f71b43cc 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -3129,6 +3129,9 @@ hns3_config_gro(struct hns3_hw *hw, bool en) struct hns3_cmd_desc desc; int ret; + if (!hns3_dev_get_support(hw, GRO)) + return 0; + hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false); req = (struct hns3_cfg_gro_status_cmd *)desc.data; -- 2.33.0