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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS3PEPF000099E1.mail.protection.outlook.com (10.167.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.18 via Frontend Transport; Mon, 11 Dec 2023 10:14:42 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 11 Dec 2023 02:14:30 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 11 Dec 2023 02:14:28 -0800 From: Xueming Li To: Dengdui Huang CC: dpdk stable Subject: patch 'net/hns3: fix multiple reset detected log' has been queued to stable release 22.11.4 Date: Mon, 11 Dec 2023 18:10:48 +0800 Message-ID: <20231211101226.2122-24-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211101226.2122-1-xuemingl@nvidia.com> References: <20231022142250.10324-1-xuemingl@nvidia.com> <20231211101226.2122-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E1:EE_|DM6PR12MB4879:EE_ X-MS-Office365-Filtering-Correlation-Id: 4f90d1d6-fe4e-4aed-1a99-08dbfa31fe10 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CAT:NONE; SFS:(13230031)(4636009)(396003)(39860400002)(136003)(346002)(376002)(230922051799003)(64100799003)(1800799012)(82310400011)(186009)(451199024)(46966006)(36840700001)(40470700004)(4001150100001)(6666004)(7696005)(2906002)(6916009)(53546011)(70586007)(70206006)(356005)(7636003)(36756003)(86362001)(40140700001)(316002)(8676002)(8936002)(4326008)(5660300002)(40480700001)(966005)(478600001)(40460700003)(55016003)(41300700001)(36860700001)(47076005)(82740400003)(6286002)(26005)(336012)(426003)(1076003)(2616005)(83380400001)(16526019)(461764006); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2023 10:14:42.4460 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f90d1d6-fe4e-4aed-1a99-08dbfa31fe10 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4879 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/13/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=65231cf278cc741a0c3076886a468429b63f1f48 Thanks. Xueming Li --- >From 65231cf278cc741a0c3076886a468429b63f1f48 Mon Sep 17 00:00:00 2001 From: Dengdui Huang Date: Fri, 27 Oct 2023 14:09:44 +0800 Subject: [PATCH] net/hns3: fix multiple reset detected log Cc: Xueming Li [ upstream commit 5be38fc6c0fc7e54d0121bab2fe93a27b8e8f7ab ] Currently, the driver proactively checks whether interrupt exist (by checking reset registers), related reset delay task is scheduled. When a reset whose level is equal to or lower than the current level is detected, there is unnecessary to add delay task and print logs. This patch fix it. Fixes: 2790c6464725 ("net/hns3: support device reset") Signed-off-by: Dengdui Huang --- drivers/net/hns3/hns3_ethdev.c | 64 ++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 27 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index feabedc458..576cc56216 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -128,42 +128,29 @@ hns3_pf_enable_irq0(struct hns3_hw *hw) } static enum hns3_evt_cause -hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay, - uint32_t *vec_val) +hns3_proc_imp_reset_event(struct hns3_adapter *hns, uint32_t *vec_val) { struct hns3_hw *hw = &hns->hw; __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B); - if (!is_delay) { - hw->reset.stats.imp_cnt++; - hns3_warn(hw, "IMP reset detected, clear reset status"); - } else { - hns3_schedule_delayed_reset(hns); - hns3_warn(hw, "IMP reset detected, don't clear reset status"); - } + hw->reset.stats.imp_cnt++; + hns3_warn(hw, "IMP reset detected, clear reset status"); return HNS3_VECTOR0_EVENT_RST; } static enum hns3_evt_cause -hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay, - uint32_t *vec_val) +hns3_proc_global_reset_event(struct hns3_adapter *hns, uint32_t *vec_val) { struct hns3_hw *hw = &hns->hw; __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B); - if (!is_delay) { - hw->reset.stats.global_cnt++; - hns3_warn(hw, "Global reset detected, clear reset status"); - } else { - hns3_schedule_delayed_reset(hns); - hns3_warn(hw, - "Global reset detected, don't clear reset status"); - } + hw->reset.stats.global_cnt++; + hns3_warn(hw, "Global reset detected, clear reset status"); return HNS3_VECTOR0_EVENT_RST; } @@ -177,14 +164,12 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) uint32_t hw_err_src_reg; uint32_t val; enum hns3_evt_cause ret; - bool is_delay; /* fetch the events from their corresponding regs */ vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); - is_delay = clearval == NULL ? true : false; /* * Assumption: If by any chance reset and mailbox events are reported * together then we will only process reset event and defer the @@ -193,13 +178,13 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) * from H/W just for the mailbox. */ if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */ - ret = hns3_proc_imp_reset_event(hns, is_delay, &val); + ret = hns3_proc_imp_reset_event(hns, &val); goto out; } /* Global reset */ if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) { - ret = hns3_proc_global_reset_event(hns, is_delay, &val); + ret = hns3_proc_global_reset_event(hns, &val); goto out; } @@ -228,10 +213,9 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) val = vector0_int_stats; ret = HNS3_VECTOR0_EVENT_OTHER; -out: - if (clearval) - *clearval = val; +out: + *clearval = val; return ret; } @@ -5539,6 +5523,32 @@ is_pf_reset_done(struct hns3_hw *hw) return true; } +static void +hns3_detect_reset_event(struct hns3_hw *hw) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + enum hns3_reset_level new_req = HNS3_NONE_RESET; + enum hns3_reset_level last_req; + uint32_t vector0_intr_state; + + last_req = hns3_get_reset_level(hns, &hw->reset.pending); + vector0_intr_state = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); + if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_intr_state) { + __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); + hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending); + new_req = HNS3_IMP_RESET; + } else if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_intr_state) { + __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); + hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending); + new_req = HNS3_GLOBAL_RESET; + } + + if (new_req != HNS3_NONE_RESET && last_req < new_req) { + hns3_schedule_delayed_reset(hns); + hns3_warn(hw, "High level reset detected, delay do reset"); + } +} + bool hns3_is_reset_pending(struct hns3_adapter *hns) { @@ -5552,7 +5562,7 @@ hns3_is_reset_pending(struct hns3_adapter *hns) if (rte_eal_process_type() != RTE_PROC_PRIMARY) return false; - hns3_check_event_cause(hns, NULL); + hns3_detect_reset_event(hw); reset = hns3_get_reset_level(hns, &hw->reset.pending); if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) { -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-12-11 17:56:23.934646000 +0800 +++ 0023-net-hns3-fix-multiple-reset-detected-log.patch 2023-12-11 17:56:22.917652300 +0800 @@ -1 +1 @@ -From 5be38fc6c0fc7e54d0121bab2fe93a27b8e8f7ab Mon Sep 17 00:00:00 2001 +From 65231cf278cc741a0c3076886a468429b63f1f48 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 5be38fc6c0fc7e54d0121bab2fe93a27b8e8f7ab ] @@ -15 +17,0 @@ -Cc: stable@dpdk.org @@ -23 +25 @@ -index 3bdce1fa4b..18afc0fa0a 100644 +index feabedc458..576cc56216 100644 @@ -26 +28 @@ -@@ -124,42 +124,29 @@ hns3_pf_enable_irq0(struct hns3_hw *hw) +@@ -128,42 +128,29 @@ hns3_pf_enable_irq0(struct hns3_hw *hw) @@ -75 +77 @@ -@@ -173,14 +160,12 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) +@@ -177,14 +164,12 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) @@ -90 +92 @@ -@@ -189,13 +174,13 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) +@@ -193,13 +178,13 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) @@ -106 +108 @@ -@@ -224,10 +209,9 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) +@@ -228,10 +213,9 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval) @@ -119 +121 @@ -@@ -5505,6 +5489,32 @@ is_pf_reset_done(struct hns3_hw *hw) +@@ -5539,6 +5523,32 @@ is_pf_reset_done(struct hns3_hw *hw) @@ -152 +154 @@ -@@ -5518,7 +5528,7 @@ hns3_is_reset_pending(struct hns3_adapter *hns) +@@ -5552,7 +5562,7 @@ hns3_is_reset_pending(struct hns3_adapter *hns)