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SFS:(13230031)(4636009)(396003)(346002)(136003)(376002)(39860400002)(230922051799003)(64100799003)(451199024)(186009)(1800799012)(82310400011)(40470700004)(46966006)(36840700001)(4326008)(83380400001)(8936002)(55016003)(40480700001)(40460700003)(8676002)(110136005)(70206006)(70586007)(54906003)(6636002)(316002)(426003)(1076003)(6286002)(16526019)(336012)(26005)(36860700001)(7696005)(82740400003)(2906002)(86362001)(47076005)(5660300002)(356005)(7636003)(2616005)(478600001)(6666004)(41300700001)(36756003)(21314003)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jan 2024 03:18:34.2396 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97e6a829-e47d-4557-ad84-08dc1d545075 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8529 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org For the case: `ethtool -L eth0 combined xxx` in VM, VQ will disable and enable without calling device close. In such case, need add drain CQ before reuse/reset event QP. Fixes: 24969c7b62 ("vdpa/mlx5: reuse event queues") Cc: stable@dpdk.org Signed-off-by: Yajun Wu Acked-by: Matan Azrad --- drivers/vdpa/mlx5/mlx5_vdpa_event.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c index 9557c1042e..32430614d5 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c @@ -244,22 +244,30 @@ mlx5_vdpa_queues_complete(struct mlx5_vdpa_priv *priv) return max; } +static void +mlx5_vdpa_drain_cq_one(struct mlx5_vdpa_priv *priv, + struct mlx5_vdpa_virtq *virtq) +{ + struct mlx5_vdpa_cq *cq = &virtq->eqp.cq; + + mlx5_vdpa_queue_complete(cq); + if (cq->cq_obj.cq) { + cq->cq_obj.cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX); + virtq->eqp.qp_pi = 0; + if (!cq->armed) + mlx5_vdpa_cq_arm(priv, cq); + } +} + void mlx5_vdpa_drain_cq(struct mlx5_vdpa_priv *priv) { + struct mlx5_vdpa_virtq *virtq; unsigned int i; for (i = 0; i < priv->caps.max_num_virtio_queues; i++) { - struct mlx5_vdpa_cq *cq = &priv->virtqs[i].eqp.cq; - - mlx5_vdpa_queue_complete(cq); - if (cq->cq_obj.cq) { - cq->cq_obj.cqes[0].wqe_counter = - rte_cpu_to_be_16(UINT16_MAX); - priv->virtqs[i].eqp.qp_pi = 0; - if (!cq->armed) - mlx5_vdpa_cq_arm(priv, cq); - } + virtq = &priv->virtqs[i]; + mlx5_vdpa_drain_cq_one(priv, virtq); } } @@ -632,6 +640,7 @@ mlx5_vdpa_event_qp_prepare(struct mlx5_vdpa_priv *priv, uint16_t desc_n, if (eqp->cq.cq_obj.cq != NULL && log_desc_n == eqp->cq.log_desc_n) { /* Reuse existing resources. */ eqp->cq.callfd = callfd; + mlx5_vdpa_drain_cq_one(priv, virtq); /* FW will set event qp to error state in q destroy. */ if (reset && !mlx5_vdpa_qps2rst2rts(eqp)) rte_write32(rte_cpu_to_be_32(RTE_BIT32(log_desc_n)), -- 2.27.0