* [PATCH v1 01/23] common/mlx5: fix duplicate read of general capabilities [not found] <20231203112543.844014-1-michaelba@nvidia.com> @ 2023-12-03 11:25 ` Michael Baum 2023-12-03 11:25 ` [PATCH v1 02/23] common/mlx5: fix query sample info capability Michael Baum ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Michael Baum @ 2023-12-03 11:25 UTC (permalink / raw) To: dev Cc: Matan Azrad, Raslan Darawsheh, Viacheslav Ovsiienko, Ori Kam, Suanming Mou, dekelp, stable General object types support is indicated in bitmap general_obj_types, which is part of HCA capabilities list. This bitmap was read multiple times, and each time a different bit was extracted. Previous patch optimized the code, reading the bitmap once into a local variable, and then extracting the required bits. However, it missed few of them which still read the bitmap for themselves. In addition, for other readings, it moved them to use local variable without removing the old reading, and they are read twice. This patch moves them all to use the local variable and removes all duplications. Fixes: 876d4702b141 ("common/mlx5: optimize read of general capabilities") Cc: dekelp@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum <michaelba@nvidia.com> --- drivers/common/mlx5/mlx5_devx_cmds.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 4d8818924a..41f6e0a727 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -966,18 +966,6 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, max_geneve_tlv_option_data_len); attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); - attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & - MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); - attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & - MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); - attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & - MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); - attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & - MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, wqe_index_ignore_cap); attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); @@ -1001,6 +989,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, /* Read the general_obj_types bitmap and extract the relevant bits. */ general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, general_obj_types); + attr->qos.flow_meter_aso_sup = + !!(general_obj_types_supported & + MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); attr->vdpa.valid = !!(general_obj_types_supported & MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); attr->vdpa.queue_counters_valid = @@ -1074,8 +1065,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); - attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & + attr->ct_offload = !!(general_obj_types_supported & MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1 02/23] common/mlx5: fix query sample info capability [not found] <20231203112543.844014-1-michaelba@nvidia.com> 2023-12-03 11:25 ` [PATCH v1 01/23] common/mlx5: fix duplicate read of general capabilities Michael Baum @ 2023-12-03 11:25 ` Michael Baum 2023-12-03 11:25 ` [PATCH v1 03/23] net/mlx5/hws: fix tunnel protocol checks Michael Baum [not found] ` <20240125133043.575860-1-michaelba@nvidia.com> 3 siblings, 0 replies; 6+ messages in thread From: Michael Baum @ 2023-12-03 11:25 UTC (permalink / raw) To: dev Cc: Matan Azrad, Raslan Darawsheh, Viacheslav Ovsiienko, Ori Kam, Suanming Mou, rongweil, stable Query sample info operation might be used by either Geneve TLV option or parse graph. Each operations can be supported regardless to another according the configured profile. In current implementation, the query sample info capability is turn on only when parse graph operation is supported adding unnecessary requirement for Geneve TLV option. This patch adds different cap for Geneve TLV option. Fixes: bc0a9303ed6a ("net/mlx5: adopt new sample ID") Cc: rongweil@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum <michaelba@nvidia.com> --- drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++-- drivers/common/mlx5/mlx5_devx_cmds.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 41f6e0a727..3eeb27fc3f 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -965,6 +965,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, max_geneve_tlv_options); attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, max_geneve_tlv_option_data_len); + attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, + query_match_sample_info); attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, wqe_index_ignore_cap); @@ -1094,8 +1096,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, (ctx, &attr->flex); if (rc) return -1; - attr->flex.query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, - query_match_sample_info); + attr->flex.query_match_sample_info = + attr->query_match_sample_info; } if (attr->crypto) { attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 7f23e925a5..b814c8becc 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -315,6 +315,7 @@ struct mlx5_hca_attr { uint32_t flow_counter_bulk_log_granularity:5; uint32_t alloc_flow_counter_pd:1; uint32_t flow_counter_access_aso:1; + uint32_t query_match_sample_info:1; uint32_t flow_access_aso_opc_mod:8; uint32_t cross_vhca:1; uint32_t lag_rx_port_affinity:1; -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1 03/23] net/mlx5/hws: fix tunnel protocol checks [not found] <20231203112543.844014-1-michaelba@nvidia.com> 2023-12-03 11:25 ` [PATCH v1 01/23] common/mlx5: fix duplicate read of general capabilities Michael Baum 2023-12-03 11:25 ` [PATCH v1 02/23] common/mlx5: fix query sample info capability Michael Baum @ 2023-12-03 11:25 ` Michael Baum [not found] ` <20240125133043.575860-1-michaelba@nvidia.com> 3 siblings, 0 replies; 6+ messages in thread From: Michael Baum @ 2023-12-03 11:25 UTC (permalink / raw) To: dev Cc: Matan Azrad, Raslan Darawsheh, Viacheslav Ovsiienko, Ori Kam, Suanming Mou, Alex Vesker, erezsh, stable From: Alex Vesker <valex@nvidia.com> Align GRE, GTPU and VXLAN tunnel protocols to fail in case the packet is already tunneled. Also use local defines for protocol UDP ports for better layering of mlx5dr API. Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer") Fixes: 5bf14a4beb1a ("net/mlx5/hws: support matching on MPLSoUDP") Cc: valex@nvidia.com Cc: erezsh@nvidia.com Cc: stable@dpdk.org Signed-off-by: Alex Vesker <valex@nvidia.com> --- drivers/net/mlx5/hws/mlx5dr_definer.c | 39 +++++++++++++-------------- 1 file changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 0b60479406..bab1869369 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -8,8 +8,9 @@ #define BAD_PORT 0xBAD #define ETH_TYPE_IPV4_VXLAN 0x0800 #define ETH_TYPE_IPV6_VXLAN 0x86DD -#define ETH_VXLAN_DEFAULT_PORT 4789 -#define IP_UDP_PORT_MPLS 6635 +#define UDP_GTPU_PORT 2152 +#define UDP_VXLAN_PORT 4789 +#define UDP_PORT_MPLS 6635 #define UDP_ROCEV2_PORT 4791 #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS) @@ -158,7 +159,7 @@ struct mlx5dr_definer_conv_data { X(SET, tcp_protocol, STE_TCP, rte_flow_item_tcp) \ X(SET_BE16, tcp_src_port, v->hdr.src_port, rte_flow_item_tcp) \ X(SET_BE16, tcp_dst_port, v->hdr.dst_port, rte_flow_item_tcp) \ - X(SET, gtp_udp_port, RTE_GTPU_UDP_PORT, rte_flow_item_gtp) \ + X(SET, gtp_udp_port, UDP_GTPU_PORT, rte_flow_item_gtp) \ X(SET_BE32, gtp_teid, v->hdr.teid, rte_flow_item_gtp) \ X(SET, gtp_msg_type, v->hdr.msg_type, rte_flow_item_gtp) \ X(SET, gtp_ext_flag, !!v->hdr.gtp_hdr_info, rte_flow_item_gtp) \ @@ -166,8 +167,8 @@ struct mlx5dr_definer_conv_data { X(SET, gtp_ext_hdr_pdu, v->hdr.type, rte_flow_item_gtp_psc) \ X(SET, gtp_ext_hdr_qfi, v->hdr.qfi, rte_flow_item_gtp_psc) \ X(SET, vxlan_flags, v->flags, rte_flow_item_vxlan) \ - X(SET, vxlan_udp_port, ETH_VXLAN_DEFAULT_PORT, rte_flow_item_vxlan) \ - X(SET, mpls_udp_port, IP_UDP_PORT_MPLS, rte_flow_item_mpls) \ + X(SET, vxlan_udp_port, UDP_VXLAN_PORT, rte_flow_item_vxlan) \ + X(SET, mpls_udp_port, UDP_PORT_MPLS, rte_flow_item_mpls) \ X(SET, source_qp, v->queue, mlx5_rte_flow_item_sq) \ X(SET, tag, v->data, rte_flow_item_tag) \ X(SET, metadata, v->data, rte_flow_item_meta) \ @@ -1170,6 +1171,12 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, const struct rte_flow_item_gtp *m = item->mask; struct mlx5dr_definer_fc *fc; + if (cd->tunnel) { + DR_LOG(ERR, "Inner GTPU item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + /* Overwrite GTPU dest port if not present */ fc = &cd->fc[DR_CALC_FNAME(L4_DPORT, false)]; if (!fc->tag_set && !cd->relaxed) { @@ -1344,9 +1351,13 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, struct mlx5dr_definer_fc *fc; bool inner = cd->tunnel; - /* In order to match on VXLAN we must match on ether_type, ip_protocol - * and l4_dport. - */ + if (inner) { + DR_LOG(ERR, "Inner VXLAN item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + + /* In order to match on VXLAN we must match on ip_protocol and l4_dport */ if (!cd->relaxed) { fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; if (!fc->tag_set) { @@ -1369,12 +1380,6 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, return 0; if (m->flags) { - if (inner) { - DR_LOG(ERR, "Inner VXLAN flags item not supported"); - rte_errno = ENOTSUP; - return rte_errno; - } - fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_FLAGS]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_vxlan_flags_set; @@ -1384,12 +1389,6 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, } if (!is_mem_zero(m->vni, 3)) { - if (inner) { - DR_LOG(ERR, "Inner VXLAN vni item not supported"); - rte_errno = ENOTSUP; - return rte_errno; - } - fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_VNI]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_vxlan_vni_set; -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
[parent not found: <20240125133043.575860-1-michaelba@nvidia.com>]
* [PATCH v2 01/23] common/mlx5: fix duplicate read of general capabilities [not found] ` <20240125133043.575860-1-michaelba@nvidia.com> @ 2024-01-25 13:30 ` Michael Baum 2024-01-25 13:30 ` [PATCH v2 02/23] common/mlx5: fix query sample info capability Michael Baum 2024-01-25 13:30 ` [PATCH v2 03/23] net/mlx5/hws: fix tunnel protocol checks Michael Baum 2 siblings, 0 replies; 6+ messages in thread From: Michael Baum @ 2024-01-25 13:30 UTC (permalink / raw) To: dev Cc: Matan Azrad, Raslan Darawsheh, Dariusz Sosnowski, Viacheslav Ovsiienko, Ori Kam, Suanming Mou, dekelp, stable General object types support is indicated in bitmap general_obj_types, which is part of HCA capabilities list. This bitmap was read multiple times, and each time a different bit was extracted. Previous patch optimized the code, reading the bitmap once into a local variable, and then extracting the required bits. However, it missed few of them which still read the bitmap for themselves. In addition, for other readings, it moved them to use local variable without removing the old reading, and they are read twice. This patch moves them all to use the local variable and removes all duplications. Fixes: 876d4702b141 ("common/mlx5: optimize read of general capabilities") Cc: dekelp@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum <michaelba@nvidia.com> Acked-by: Suanming Mou <suanmingm@nvidia.com> --- drivers/common/mlx5/mlx5_devx_cmds.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 3a894f894a..faa38a9f95 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -966,18 +966,6 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, max_geneve_tlv_option_data_len); attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); - attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & - MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); - attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & - MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); - attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & - MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); - attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & - MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, wqe_index_ignore_cap); attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); @@ -1001,6 +989,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, /* Read the general_obj_types bitmap and extract the relevant bits. */ general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, general_obj_types); + attr->qos.flow_meter_aso_sup = + !!(general_obj_types_supported & + MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); attr->vdpa.valid = !!(general_obj_types_supported & MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); attr->vdpa.queue_counters_valid = @@ -1074,8 +1065,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); - attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, - general_obj_types) & + attr->ct_offload = !!(general_obj_types_supported & MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 02/23] common/mlx5: fix query sample info capability [not found] ` <20240125133043.575860-1-michaelba@nvidia.com> 2024-01-25 13:30 ` [PATCH v2 01/23] common/mlx5: fix duplicate read of general capabilities Michael Baum @ 2024-01-25 13:30 ` Michael Baum 2024-01-25 13:30 ` [PATCH v2 03/23] net/mlx5/hws: fix tunnel protocol checks Michael Baum 2 siblings, 0 replies; 6+ messages in thread From: Michael Baum @ 2024-01-25 13:30 UTC (permalink / raw) To: dev Cc: Matan Azrad, Raslan Darawsheh, Dariusz Sosnowski, Viacheslav Ovsiienko, Ori Kam, Suanming Mou, rongweil, stable Query sample info operation might be used by either Geneve TLV option or parse graph. Each operations can be supported regardless to another according the configured profile. In current implementation, the query sample info capability is turn on only when parse graph operation is supported adding unnecessary requirement for Geneve TLV option. This patch adds different cap for Geneve TLV option. Fixes: bc0a9303ed6a ("net/mlx5: adopt new sample ID") Cc: rongweil@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum <michaelba@nvidia.com> Acked-by: Suanming Mou <suanmingm@nvidia.com> --- drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++-- drivers/common/mlx5/mlx5_devx_cmds.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index faa38a9f95..9b1cfcc135 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -965,6 +965,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, max_geneve_tlv_options); attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, max_geneve_tlv_option_data_len); + attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, + query_match_sample_info); attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, wqe_index_ignore_cap); @@ -1094,8 +1096,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, (ctx, &attr->flex); if (rc) return -1; - attr->flex.query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, - query_match_sample_info); + attr->flex.query_match_sample_info = + attr->query_match_sample_info; } if (attr->crypto) { attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts) || diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 4a6008dc1a..0c5727b669 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -316,6 +316,7 @@ struct mlx5_hca_attr { uint32_t flow_counter_bulk_log_granularity:5; uint32_t alloc_flow_counter_pd:1; uint32_t flow_counter_access_aso:1; + uint32_t query_match_sample_info:1; uint32_t flow_access_aso_opc_mod:8; uint32_t cross_vhca:1; uint32_t lag_rx_port_affinity:1; -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 03/23] net/mlx5/hws: fix tunnel protocol checks [not found] ` <20240125133043.575860-1-michaelba@nvidia.com> 2024-01-25 13:30 ` [PATCH v2 01/23] common/mlx5: fix duplicate read of general capabilities Michael Baum 2024-01-25 13:30 ` [PATCH v2 02/23] common/mlx5: fix query sample info capability Michael Baum @ 2024-01-25 13:30 ` Michael Baum 2 siblings, 0 replies; 6+ messages in thread From: Michael Baum @ 2024-01-25 13:30 UTC (permalink / raw) To: dev Cc: Matan Azrad, Raslan Darawsheh, Dariusz Sosnowski, Viacheslav Ovsiienko, Ori Kam, Suanming Mou, Alex Vesker, erezsh, stable From: Alex Vesker <valex@nvidia.com> Align GRE, GTPU and VXLAN tunnel protocols to fail in case the packet is already tunneled. Also use local defines for protocol UDP ports for better layering of mlx5dr API. Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer") Fixes: 5bf14a4beb1a ("net/mlx5/hws: support matching on MPLSoUDP") Cc: valex@nvidia.com Cc: erezsh@nvidia.com Cc: stable@dpdk.org Signed-off-by: Alex Vesker <valex@nvidia.com> Acked-by: Suanming Mou <suanmingm@nvidia.com> --- drivers/net/mlx5/hws/mlx5dr_definer.c | 43 +++++++++++++-------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 750eb9c7c6..219bffd3b5 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -8,9 +8,10 @@ #define BAD_PORT 0xBAD #define ETH_TYPE_IPV4_VXLAN 0x0800 #define ETH_TYPE_IPV6_VXLAN 0x86DD -#define ETH_VXLAN_DEFAULT_PORT 4789 -#define ETH_VXLAN_GPE_DEFAULT_PORT 4790 -#define IP_UDP_PORT_MPLS 6635 +#define UDP_VXLAN_PORT 4789 +#define UDP_VXLAN_GPE_PORT 4790 +#define UDP_GTPU_PORT 2152 +#define UDP_PORT_MPLS 6635 #define UDP_ROCEV2_PORT 4791 #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS) @@ -159,7 +160,7 @@ struct mlx5dr_definer_conv_data { X(SET, tcp_protocol, STE_TCP, rte_flow_item_tcp) \ X(SET_BE16, tcp_src_port, v->hdr.src_port, rte_flow_item_tcp) \ X(SET_BE16, tcp_dst_port, v->hdr.dst_port, rte_flow_item_tcp) \ - X(SET, gtp_udp_port, RTE_GTPU_UDP_PORT, rte_flow_item_gtp) \ + X(SET, gtp_udp_port, UDP_GTPU_PORT, rte_flow_item_gtp) \ X(SET_BE32, gtp_teid, v->hdr.teid, rte_flow_item_gtp) \ X(SET, gtp_msg_type, v->hdr.msg_type, rte_flow_item_gtp) \ X(SET, gtp_ext_flag, !!v->hdr.gtp_hdr_info, rte_flow_item_gtp) \ @@ -167,12 +168,12 @@ struct mlx5dr_definer_conv_data { X(SET, gtp_ext_hdr_pdu, v->hdr.type, rte_flow_item_gtp_psc) \ X(SET, gtp_ext_hdr_qfi, v->hdr.qfi, rte_flow_item_gtp_psc) \ X(SET, vxlan_flags, v->flags, rte_flow_item_vxlan) \ - X(SET, vxlan_udp_port, ETH_VXLAN_DEFAULT_PORT, rte_flow_item_vxlan) \ - X(SET, vxlan_gpe_udp_port, ETH_VXLAN_GPE_DEFAULT_PORT, rte_flow_item_vxlan_gpe) \ + X(SET, vxlan_udp_port, UDP_VXLAN_PORT, rte_flow_item_vxlan) \ + X(SET, vxlan_gpe_udp_port, UDP_VXLAN_GPE_PORT, rte_flow_item_vxlan_gpe) \ X(SET, vxlan_gpe_flags, v->flags, rte_flow_item_vxlan_gpe) \ X(SET, vxlan_gpe_protocol, v->protocol, rte_flow_item_vxlan_gpe) \ X(SET, vxlan_gpe_rsvd1, v->rsvd1, rte_flow_item_vxlan_gpe) \ - X(SET, mpls_udp_port, IP_UDP_PORT_MPLS, rte_flow_item_mpls) \ + X(SET, mpls_udp_port, UDP_PORT_MPLS, rte_flow_item_mpls) \ X(SET, source_qp, v->queue, mlx5_rte_flow_item_sq) \ X(SET, tag, v->data, rte_flow_item_tag) \ X(SET, metadata, v->data, rte_flow_item_meta) \ @@ -1198,6 +1199,12 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, const struct rte_flow_item_gtp *m = item->mask; struct mlx5dr_definer_fc *fc; + if (cd->tunnel) { + DR_LOG(ERR, "Inner GTPU item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + /* Overwrite GTPU dest port if not present */ fc = &cd->fc[DR_CALC_FNAME(L4_DPORT, false)]; if (!fc->tag_set && !cd->relaxed) { @@ -1372,9 +1379,13 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, struct mlx5dr_definer_fc *fc; bool inner = cd->tunnel; - /* In order to match on VXLAN we must match on ether_type, ip_protocol - * and l4_dport. - */ + if (inner) { + DR_LOG(ERR, "Inner VXLAN item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + + /* In order to match on VXLAN we must match on ip_protocol and l4_dport */ if (!cd->relaxed) { fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; if (!fc->tag_set) { @@ -1397,12 +1408,6 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, return 0; if (m->flags) { - if (inner) { - DR_LOG(ERR, "Inner VXLAN flags item not supported"); - rte_errno = ENOTSUP; - return rte_errno; - } - fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_FLAGS]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_vxlan_flags_set; @@ -1412,12 +1417,6 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, } if (!is_mem_zero(m->vni, 3)) { - if (inner) { - DR_LOG(ERR, "Inner VXLAN vni item not supported"); - rte_errno = ENOTSUP; - return rte_errno; - } - fc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_VNI]; fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_vxlan_vni_set; -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
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[not found] <20231203112543.844014-1-michaelba@nvidia.com>
2023-12-03 11:25 ` [PATCH v1 01/23] common/mlx5: fix duplicate read of general capabilities Michael Baum
2023-12-03 11:25 ` [PATCH v1 02/23] common/mlx5: fix query sample info capability Michael Baum
2023-12-03 11:25 ` [PATCH v1 03/23] net/mlx5/hws: fix tunnel protocol checks Michael Baum
[not found] ` <20240125133043.575860-1-michaelba@nvidia.com>
2024-01-25 13:30 ` [PATCH v2 01/23] common/mlx5: fix duplicate read of general capabilities Michael Baum
2024-01-25 13:30 ` [PATCH v2 02/23] common/mlx5: fix query sample info capability Michael Baum
2024-01-25 13:30 ` [PATCH v2 03/23] net/mlx5/hws: fix tunnel protocol checks Michael Baum
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