patches for DPDK stable branches
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From: Gregory Etelson <getelson@nvidia.com>
To: <dev@dpdk.org>
Cc: <getelson@nvidia.com>, <mkashani@nvidia.com>,
	<rasland@nvidia.com>, <stable@dpdk.org>,
	Dariusz Sosnowski <dsosnowski@nvidia.com>,
	"Viacheslav Ovsiienko" <viacheslavo@nvidia.com>,
	Ori Kam <orika@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>,
	Matan Azrad <matan@nvidia.com>
Subject: [PATCH] net/mlx5: fix VID assignment in VLAN modify
Date: Fri, 1 Mar 2024 08:04:48 +0200	[thread overview]
Message-ID: <20240301060448.88350-1-getelson@nvidia.com> (raw)

PMD uses MODIFY_FIELD to implement standalone OF_SET_VLAN_VID flow
action.
PMD assigned immediate VLAN Id value to the `.level` member of the
`rte_flow_action_modify_data` structure instead of `.value`.
That assignment has worked because both members had the same offset in
the hosting structure.

The patch assigns VLAN Id directly to `.value`

Fixes: 773ca0e91ba1 ("net/mlx5: support VLAN push/pop/modify with HWS")
Cc: stable@dpdk.org (backport)

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_hw.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index a87bb52c06..027b0e084d 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -6863,7 +6863,6 @@ flow_hw_set_vlan_vid(struct rte_eth_dev *dev,
 			rm[set_vlan_vid_ix].conf)->vlan_vid != 0);
 	const struct rte_flow_action_of_set_vlan_vid *conf =
 		ra[set_vlan_vid_ix].conf;
-	rte_be16_t vid = masked ? conf->vlan_vid : 0;
 	int width = mlx5_flow_item_field_width(dev, RTE_FLOW_FIELD_VLAN_ID, 0,
 					       NULL, &error);
 	*spec = (typeof(*spec)) {
@@ -6874,8 +6873,6 @@ flow_hw_set_vlan_vid(struct rte_eth_dev *dev,
 		},
 		.src = {
 			.field = RTE_FLOW_FIELD_VALUE,
-			.level = vid,
-			.offset = 0,
 		},
 		.width = width,
 	};
@@ -6887,11 +6884,15 @@ flow_hw_set_vlan_vid(struct rte_eth_dev *dev,
 		},
 		.src = {
 			.field = RTE_FLOW_FIELD_VALUE,
-			.level = masked ? (1U << width) - 1 : 0,
-			.offset = 0,
 		},
 		.width = 0xffffffff,
 	};
+	if (masked) {
+		uint32_t mask_val = 0xffffffff;
+
+		rte_memcpy(spec->src.value, &conf->vlan_vid, sizeof(conf->vlan_vid));
+		rte_memcpy(mask->src.value, &mask_val, sizeof(mask_val));
+	}
 	ra[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
 	ra[set_vlan_vid_ix].conf = spec;
 	rm[set_vlan_vid_ix].type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD;
@@ -6918,8 +6919,6 @@ flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
 		},
 		.src = {
 			.field = RTE_FLOW_FIELD_VALUE,
-			.level = vid,
-			.offset = 0,
 		},
 		.width = width,
 	};
@@ -6928,6 +6927,7 @@ flow_hw_set_vlan_vid_construct(struct rte_eth_dev *dev,
 		.conf = &conf
 	};
 
+	rte_memcpy(conf.src.value, &vid, sizeof(vid));
 	return flow_hw_modify_field_construct(mhdr_cmd, act_data, hw_acts, &modify_action);
 }
 
-- 
2.39.2


             reply	other threads:[~2024-03-01  6:05 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-01  6:04 Gregory Etelson [this message]
2024-03-12  8:06 ` Raslan Darawsheh

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