From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 789AC43E57 for ; Sat, 13 Apr 2024 14:59:42 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6728A40EAB; Sat, 13 Apr 2024 14:59:42 +0200 (CEST) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2041.outbound.protection.outlook.com [40.107.237.41]) by mails.dpdk.org (Postfix) with ESMTP id 9F32040E2D for ; Sat, 13 Apr 2024 14:59:40 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kbu8E4bEgsf5isXmrCzvn8M/npowWSx7pQ52M65bBmsCD7vyy09ipQ+68qfbioy0BzCaaiw6idA+zPyWOe2XtEcVIV74XPniRAsrmTA7e2hKddbXtgPHmOfe4zXmLPCwWOehx6ViIoUduAfp4lnucF1/um6ddzChcg9NrJA0M4ImyvSuOnM4fvwVi3VcyidM8XeKZjQXN5A8VmDQt8Z3vqap3u8gDJIGTdwF9VoR/itiHWPtrhD+FXk88+VUanv3nfuEU+Lx5mMK5xdXpt8l/uAw6C4btFjm52pytDp4RGz5ZvoqoOJTuJ//XFzO/G3DTerZI3jPI3HQeRIkg3Efww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=juPXxOyd1DeggU+KbhDpHWsHfDYtUoVPBfi0CP/JxE0=; b=SObDultuiX9FFCp6Etoxcq3mkW5Qc/QQoFZ7dFQxFJaSWnTkMn6HdKFBFdgyHhWZdaw+j3d0olJXhEEuUEHp6v2njvVje0FrGXXuPKkdyasuX6l8eAhpKsEJ5sklyEDXbAcFRfyut+ogiZ6Ax2ALKfpikaZv/4rn84L1ttOylSd1WaUDcMO3dTu4S0FVcA/hBRyfUVlnNbumW3jlyIIZISYhkTRXbLv7VxlO6tUhplGFgujJW5zXt/T1DMXesdcNJeZfzT1IVLMxUUk/rAInaxJ3GOpq3lUq6QsX4rkFx40w8suhJvmpS0RUgCyupLuq3ZukPbIe4TrOEN1CJRcR6A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=juPXxOyd1DeggU+KbhDpHWsHfDYtUoVPBfi0CP/JxE0=; b=IaKM5gqTVtVa/cYP0ZB9UKWjpscw36qAQCzdyuZWDqNCuQ3e9v7IZ8ry+Pb3N+zYDYTORFJvh7K4jw3D/1LDc0rqOle5mWyNdc8/gKngEsK5CLmw4xU4Ks/kILpwN8HgnO8G+s4S8wX+hNCTFExz9GgGxUeU9C4HPdm2hn3yvhe0IHj9p7DBFc94fA1gNgT01fY91o1GEw8qCHAx4bnui1qzn6cDVzYVVgz+UWrBdcKzD+JXWQV6qtoQ3x312O61OnpF51AREyA62Yt3hWoiRMxWLLrbWQy+XQnJ7nHnsp5CdRgcZ/pPo772CAxYykXwaAeCoj7INMnkbkFo3g6oSw== Received: from MW4PR03CA0254.namprd03.prod.outlook.com (2603:10b6:303:b4::19) by PH7PR12MB7331.namprd12.prod.outlook.com (2603:10b6:510:20e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.46; Sat, 13 Apr 2024 12:59:37 +0000 Received: from MWH0EPF000A672F.namprd04.prod.outlook.com (2603:10b6:303:b4:cafe::8c) by MW4PR03CA0254.outlook.office365.com (2603:10b6:303:b4::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7472.22 via Frontend Transport; Sat, 13 Apr 2024 12:59:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by MWH0EPF000A672F.mail.protection.outlook.com (10.167.249.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7452.22 via Frontend Transport; Sat, 13 Apr 2024 12:59:37 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sat, 13 Apr 2024 05:59:26 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Sat, 13 Apr 2024 05:59:24 -0700 From: Xueming Li To: Dariusz Sosnowski CC: Suanming Mou , dpdk stable Subject: patch 'net/mlx5: fix flow configure validation' has been queued to stable release 23.11.1 Date: Sat, 13 Apr 2024 20:49:44 +0800 Message-ID: <20240413125005.725659-104-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240413125005.725659-1-xuemingl@nvidia.com> References: <20240305094757.439387-1-xuemingl@nvidia.com> <20240413125005.725659-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A672F:EE_|PH7PR12MB7331:EE_ X-MS-Office365-Filtering-Correlation-Id: 22acbffd-97ca-4843-2974-08dc5bb9932b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hswuldSNEaqCjf96n4xVzrq1hZgbqSAX+UF5fx1VGbOlNqkK2doYlxx+HxUk1vjAxBd+hBLNv2nsWJewfomTDS+MM6FgUCF04cQZkZa1rGlwadL96+wvZHJj0IGrkv2IURjn1EmpY13qq5oTxvnW6UPPLNAJ+1p8gJFNmWxOqPiIpQGHp8Scx2KJ/Jg2JKG/DJRUVGXD8D7PGt0N7R7GUXJ3yEszZjz4afA++7kNFqbjJSNd8yr6UPDi8P7OvLMRwcjnU9bizuIdTDCheqvKwPidkuaZpJCHl90jKZ2k0L176BJINwU6F87sUypGEodGGNLbFFAZwO8u0Fj0eWV0wR2wak4JL4Uyi91rKcjLOdzedNZwWEMEH0nCGLsqKWQhXXbiJOw/piLfNpywc1tNGirW0spxiBD5X0aI1EXQirYzo0vtb//x5MnIBnkjvFcAEEQA+74c02PtAgMhkbRQOHUsg25xbqoXE/dI/f/kS2wqTv/YLAuKWTYGDlp0Q8Ien/xIkB0bM0Ledpf2NehCMyC9go4RwJn2PV7XiCW9fe17FXMwGUUIAaO496WW/Kb0x/D5uE+yG/rifuAqjjWetKf/4L7+xePDcBmgWej7dVSzTOvFtA6bQQZOEXLW0/weYiJ+X0N4OrcHwEjx6YVhQBYZrL4cwyVHsK+uiCq4RPT7F04dWr8v1rnpakOciI6ISEtLiD+iIZRDBvEcIJfm0s418CyHQulDC+ywn1rGsgqpEgl+77WEMsST5mG317UL X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(1800799015)(376005)(82310400014)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2024 12:59:37.4987 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22acbffd-97ca-4843-2974-08dc5bb9932b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7331 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.1 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 04/15/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=8117b4b2f7fa51f50686aa90939b8d8ac41a4ddc Thanks. Xueming Li --- >From 8117b4b2f7fa51f50686aa90939b8d8ac41a4ddc Mon Sep 17 00:00:00 2001 From: Dariusz Sosnowski Date: Wed, 6 Mar 2024 21:21:50 +0100 Subject: [PATCH] net/mlx5: fix flow configure validation Cc: Xueming Li [ upstream commit ff9433b578195be8c6cb44443ad199defdbf3c99 ] There's an existing limitation in mlx5 PMD, that all configured flow queues must have the same size. Even though this condition is checked, some allocations are done before that. This lead to segmentation fault during rollback on error in rte_flow_configure() implementation. This patch fixes that by reorganizing validation, so that configuration options are validated before any allocations are done and necessary checks for NULL are added to error rollback. Bugzilla ID: 1199 Fixes: b401400db24e ("net/mlx5: add port flow configuration") Signed-off-by: Dariusz Sosnowski Acked-by: Suanming Mou --- drivers/net/mlx5/mlx5_flow_hw.c | 58 +++++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 17 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 938d9b5824..a54075ed7e 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -9291,6 +9291,38 @@ flow_hw_compare_config(const struct mlx5_flow_hw_attr *hw_attr, return true; } +static int +flow_hw_validate_attributes(const struct rte_flow_port_attr *port_attr, + uint16_t nb_queue, + const struct rte_flow_queue_attr *queue_attr[], + struct rte_flow_error *error) +{ + uint32_t size; + unsigned int i; + + if (port_attr == NULL) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Port attributes must be non-NULL"); + + if (nb_queue == 0) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "At least one flow queue is required"); + + if (queue_attr == NULL) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "Queue attributes must be non-NULL"); + + size = queue_attr[0]->size; + for (i = 1; i < nb_queue; ++i) { + if (queue_attr[i]->size != size) + return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "All flow queues must have the same size"); + } + + return 0; +} + /** * Configure port HWS resources. * @@ -9342,10 +9374,8 @@ flow_hw_configure(struct rte_eth_dev *dev, int ret = 0; uint32_t action_flags; - if (!port_attr || !nb_queue || !queue_attr) { - rte_errno = EINVAL; - goto err; - } + if (flow_hw_validate_attributes(port_attr, nb_queue, queue_attr, error)) + return -rte_errno; /* * Calling rte_flow_configure() again is allowed if and only if * provided configuration matches the initially provided one. @@ -9392,14 +9422,6 @@ flow_hw_configure(struct rte_eth_dev *dev, /* Allocate the queue job descriptor LIFO. */ mem_size = sizeof(priv->hw_q[0]) * nb_q_updated; for (i = 0; i < nb_q_updated; i++) { - /* - * Check if the queues' size are all the same as the - * limitation from HWS layer. - */ - if (_queue_attr[i]->size != _queue_attr[0]->size) { - rte_errno = EINVAL; - goto err; - } mem_size += (sizeof(struct mlx5_hw_q_job *) + sizeof(struct mlx5_hw_q_job) + sizeof(uint8_t) * MLX5_ENCAP_MAX_LEN + @@ -9681,12 +9703,14 @@ err: flow_hw_destroy_vlan(dev); if (dr_ctx) claim_zero(mlx5dr_context_close(dr_ctx)); - for (i = 0; i < nb_q_updated; i++) { - rte_ring_free(priv->hw_q[i].indir_iq); - rte_ring_free(priv->hw_q[i].indir_cq); + if (priv->hw_q) { + for (i = 0; i < nb_q_updated; i++) { + rte_ring_free(priv->hw_q[i].indir_iq); + rte_ring_free(priv->hw_q[i].indir_cq); + } + mlx5_free(priv->hw_q); + priv->hw_q = NULL; } - mlx5_free(priv->hw_q); - priv->hw_q = NULL; if (priv->acts_ipool) { mlx5_ipool_destroy(priv->acts_ipool); priv->acts_ipool = NULL; -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-04-13 20:43:08.204017644 +0800 +++ 0104-net-mlx5-fix-flow-configure-validation.patch 2024-04-13 20:43:05.107753788 +0800 @@ -1 +1 @@ -From ff9433b578195be8c6cb44443ad199defdbf3c99 Mon Sep 17 00:00:00 2001 +From 8117b4b2f7fa51f50686aa90939b8d8ac41a4ddc Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit ff9433b578195be8c6cb44443ad199defdbf3c99 ] @@ -17 +19,0 @@ -Cc: stable@dpdk.org @@ -22,2 +24,2 @@ - drivers/net/mlx5/mlx5_flow_hw.c | 62 +++++++++++++++++++++++---------- - 1 file changed, 43 insertions(+), 19 deletions(-) + drivers/net/mlx5/mlx5_flow_hw.c | 58 +++++++++++++++++++++++---------- + 1 file changed, 41 insertions(+), 17 deletions(-) @@ -26 +28 @@ -index d88959e36d..35f1ed7a03 100644 +index 938d9b5824..a54075ed7e 100644 @@ -29,2 +31,2 @@ -@@ -10289,6 +10289,38 @@ mlx5_hwq_ring_create(uint16_t port_id, uint32_t queue, uint32_t size, const char - RING_F_SP_ENQ | RING_F_SC_DEQ | RING_F_EXACT_SZ); +@@ -9291,6 +9291,38 @@ flow_hw_compare_config(const struct mlx5_flow_hw_attr *hw_attr, + return true; @@ -68 +70 @@ -@@ -10340,10 +10372,8 @@ flow_hw_configure(struct rte_eth_dev *dev, +@@ -9342,10 +9374,8 @@ flow_hw_configure(struct rte_eth_dev *dev, @@ -81 +83 @@ -@@ -10390,14 +10420,6 @@ flow_hw_configure(struct rte_eth_dev *dev, +@@ -9392,14 +9422,6 @@ flow_hw_configure(struct rte_eth_dev *dev, @@ -94,6 +96,6 @@ - sizeof(struct mlx5_hw_q_job)) * _queue_attr[i]->size; - } -@@ -10679,14 +10701,16 @@ err: - __atomic_fetch_sub(&host_priv->shared_refcnt, 1, __ATOMIC_RELAXED); - priv->shared_host = NULL; - } + sizeof(struct mlx5_hw_q_job) + + sizeof(uint8_t) * MLX5_ENCAP_MAX_LEN + +@@ -9681,12 +9703,14 @@ err: + flow_hw_destroy_vlan(dev); + if (dr_ctx) + claim_zero(mlx5dr_context_close(dr_ctx)); @@ -103,2 +104,0 @@ -- rte_ring_free(priv->hw_q[i].flow_transfer_pending); -- rte_ring_free(priv->hw_q[i].flow_transfer_completed); @@ -109,2 +108,0 @@ -+ rte_ring_free(priv->hw_q[i].flow_transfer_pending); -+ rte_ring_free(priv->hw_q[i].flow_transfer_completed);