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From: Michael Baum <michaelba@nvidia.com>
To: <dev@dpdk.org>
Cc: Matan Azrad <matan@nvidia.com>,
	Dariusz Sosnowski <dsosnowski@nvidia.com>,
	 Raslan Darawsheh <rasland@nvidia.com>,
	Viacheslav Ovsiienko <viacheslavo@nvidia.com>,
	Ori Kam <orika@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>,
	<valex@nvidia.com>, <stable@dpdk.org>
Subject: [PATCH 2/4] net/mlx5/hws: fix GENEVE option class partial mask
Date: Tue, 16 Apr 2024 18:30:52 +0300	[thread overview]
Message-ID: <20240416153054.3216706-3-michaelba@nvidia.com> (raw)
In-Reply-To: <20240416153054.3216706-1-michaelba@nvidia.com>

When GENEVE option parser is configured, the class field has 3 optional
modes:
1. ignored - ignore this field.
2. fixed - this field is part of option identifier along with type
	   field. In this mode, the exact value is provided in "spec"
	   field during pattern template creation and mask must be 0xffff.
3. matchable - class field isn't part of the identifier and only mask is
	       provided in pattern template creation. The mask can be
	       any value like all other fields.

In current implementation, when class mask isn't 0, pattern template
creation is failed for mask != 0xffff regardless to class mode.

This patch fixes this validation to be only when class mode is fixed.

Fixes: 8f8dad4289e0 ("net/mlx5/hws: support GENEVE options matching")
Cc: valex@nvidia.com
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 35a2ed2048..f1f544deab 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -2500,11 +2500,6 @@ mlx5dr_definer_conv_item_geneve_opt(struct mlx5dr_definer_conv_data *cd,
 		goto out_not_supp;
 	}
 
-	if (m->option_class && m->option_class != RTE_BE16(UINT16_MAX)) {
-		DR_LOG(ERR, "Geneve option class has invalid mask");
-		goto out_not_supp;
-	}
-
 	ret = mlx5_get_geneve_hl_data(cd->ctx,
 				      v->option_type,
 				      v->option_class,
@@ -2517,6 +2512,11 @@ mlx5dr_definer_conv_item_geneve_opt(struct mlx5dr_definer_conv_data *cd,
 		goto out_not_supp;
 	}
 
+	if (ok_bit_on_class && m->option_class != RTE_BE16(UINT16_MAX)) {
+		DR_LOG(ERR, "Geneve option class has invalid mask");
+		goto out_not_supp;
+	}
+
 	if (!ok_bit_on_class && m->option_class) {
 		/* DW0 is used, we will match type, class */
 		if (!num_of_dws || hl_dws[0].dw_mask != UINT32_MAX) {
-- 
2.25.1


      parent reply	other threads:[~2024-04-16 15:32 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20240416153054.3216706-1-michaelba@nvidia.com>
2024-04-16 15:30 ` [PATCH 1/4] net/mlx5: fix secondary process port close Michael Baum
2024-04-16 15:30 ` Michael Baum [this message]

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