From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 143B0454E8 for ; Tue, 25 Jun 2024 01:59:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0F4064026F; Tue, 25 Jun 2024 01:59:25 +0200 (CEST) Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) by mails.dpdk.org (Postfix) with ESMTP id 6BD13400EF for ; Tue, 25 Jun 2024 01:59:23 +0200 (CEST) Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-3650f2e540dso3274843f8f.0 for ; Mon, 24 Jun 2024 16:59:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1719273563; x=1719878363; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ab6926FLM50DYVnLE31sh5sJKbcwnQAszuusib5eInY=; b=XMS6AF62QN+LHVhB4SsPvlWFDNenIOeH9+hXsXhnv2MYXaVS2FaRaLgcs+jKZi6Nd6 kZW8f8NWdltg1mkuMVLYrC7Dm8IHelZ9NKiC9tAFBc73ary3y3YSXuKyHb+plDwz9/UA M5w6yft1MkB5GiYmiQTqzvPcZLJSuBQ+slVOS1J1JrZR5Ev2Z+hXYk89pOW7Fx6+IjyC lLsTvV7LJXSeNuPHyThpVVUD2CSdMqnLOMmfgs0rxmNZFexp1e+9y0YTnzQzsZqawq+o Yw18Hdwj/7Anz0fKokqvAP54nU8T+IMjNZLog29FBi99BpuxvjGNtPBO9oTTzWWRP/if ZOOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719273563; x=1719878363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ab6926FLM50DYVnLE31sh5sJKbcwnQAszuusib5eInY=; b=fWxN9+wCdrk0JcrZoucflkTmOpx0SaJvYhGmy2JjKd7Ps7HG0kZvfLjgO9GEpXWvlk 8cfrCl1w3VMlcMGTczGedJlq5NaJI9ymwJD4pvSXsdkl1tRHat9f22vW295S3yFbhaUx tacOXVbYOI6HgDsQpUJ3zE4iv3/FP5rtzTZyc7Aq83iAdTsP/Umv5kHll86asTSHcFC3 WM51BSnQ5nAwUpio+xslVgn7ahRMr6qO1TGvmrGyB18a2O0FWfLL+XxDZSc7uI31kCpC DWR6lZOCEUBW/3va8l4YZ8YExY4f3dRMcopU7ffgMpGh8QQRBpkwJWDhUDFCdUSOh+X9 j+yg== X-Forwarded-Encrypted: i=1; AJvYcCWnsAetAbApkNQiK2S4QVukdTG5XQtUYIHLPBhv1l3+8J37V45ajgacK3QST+ey4YKohGyIPaE/lV7NsUU5XV0= X-Gm-Message-State: AOJu0Yx6lAg1dJV8eiI99xGywzxg1WyG6O+qnQlVKdOq4xq5ONf38DbA A3UiP/8DeWGQAEMKfk432QMKH7NDA2aMXuGo9yOSu/uzfhOtCXR0 X-Google-Smtp-Source: AGHT+IHqf7eMv87/17/6A2hnKoF3qUKk3Tz+A0Z73yCZTILw4VJl44PytPh8QHSzMwX4NAs0KsSKWw== X-Received: by 2002:a5d:46ca:0:b0:362:1b1:bdea with SMTP id ffacd0b85a97d-366e94d9998mr4130511f8f.8.1719273562702; Mon, 24 Jun 2024 16:59:22 -0700 (PDT) Received: from localhost ([137.220.120.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-366389b8628sm11303059f8f.41.2024.06.24.16.59.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jun 2024 16:59:22 -0700 (PDT) From: luca.boccassi@gmail.com To: David Marchand Cc: Bruce Richardson , Patrick Robb , Thomas Monjalon , dpdk stable Subject: patch 'bus/pci: fix build with musl 1.2.4 / Alpine 3.19' has been queued to stable release 22.11.6 Date: Tue, 25 Jun 2024 00:57:48 +0100 Message-Id: <20240624235907.885628-2-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240624235907.885628-1-luca.boccassi@gmail.com> References: <20240624235907.885628-1-luca.boccassi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 06/27/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/bluca/dpdk-stable This queued commit can be viewed at: https://github.com/bluca/dpdk-stable/commit/502049c8b3e997a10a3e77ad87d714ec2df63235 Thanks. Luca Boccassi --- >From 502049c8b3e997a10a3e77ad87d714ec2df63235 Mon Sep 17 00:00:00 2001 From: David Marchand Date: Mon, 29 Apr 2024 12:00:59 +0200 Subject: [PATCH] bus/pci: fix build with musl 1.2.4 / Alpine 3.19 [ upstream commit 884f83ccf74b5364430d3b21c653d5f6e359e091 ] Following an upgrade of musl, pread64/pwrite64 wrappers are not provided anymore. Switch to POSIX pread/pwrite. Bugzilla ID: 1422 Signed-off-by: David Marchand Acked-by: Bruce Richardson Tested-by: Patrick Robb Tested-by: Thomas Monjalon --- drivers/bus/pci/linux/pci_vfio.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c index fe83e1a04e..44c132ae8a 100644 --- a/drivers/bus/pci/linux/pci_vfio.c +++ b/drivers/bus/pci/linux/pci_vfio.c @@ -53,7 +53,7 @@ pci_vfio_read_config(const struct rte_intr_handle *intr_handle, if (vfio_dev_fd < 0) return -1; - return pread64(vfio_dev_fd, buf, len, + return pread(vfio_dev_fd, buf, len, VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs); } @@ -66,7 +66,7 @@ pci_vfio_write_config(const struct rte_intr_handle *intr_handle, if (vfio_dev_fd < 0) return -1; - return pwrite64(vfio_dev_fd, buf, len, + return pwrite(vfio_dev_fd, buf, len, VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs); } @@ -80,7 +80,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table) uint8_t cap_id, cap_offset; /* read PCI capability pointer from config space */ - ret = pread64(fd, ®, sizeof(reg), + ret = pread(fd, ®, sizeof(reg), VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + PCI_CAPABILITY_LIST); if (ret != sizeof(reg)) { @@ -95,7 +95,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table) while (cap_offset) { /* read PCI capability ID */ - ret = pread64(fd, ®, sizeof(reg), + ret = pread(fd, ®, sizeof(reg), VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + cap_offset); if (ret != sizeof(reg)) { @@ -109,7 +109,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table) /* if we haven't reached MSI-X, check next capability */ if (cap_id != PCI_CAP_ID_MSIX) { - ret = pread64(fd, ®, sizeof(reg), + ret = pread(fd, ®, sizeof(reg), VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + cap_offset); if (ret != sizeof(reg)) { @@ -126,7 +126,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table) /* else, read table offset */ else { /* table offset resides in the next 4 bytes */ - ret = pread64(fd, ®, sizeof(reg), + ret = pread(fd, ®, sizeof(reg), VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + cap_offset + 4); if (ret != sizeof(reg)) { @@ -135,7 +135,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table) return -1; } - ret = pread64(fd, &flags, sizeof(flags), + ret = pread(fd, &flags, sizeof(flags), VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + cap_offset + 2); if (ret != sizeof(flags)) { @@ -162,7 +162,7 @@ pci_vfio_enable_bus_memory(int dev_fd) uint16_t cmd; int ret; - ret = pread64(dev_fd, &cmd, sizeof(cmd), + ret = pread(dev_fd, &cmd, sizeof(cmd), VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + PCI_COMMAND); @@ -175,7 +175,7 @@ pci_vfio_enable_bus_memory(int dev_fd) return 0; cmd |= PCI_COMMAND_MEMORY; - ret = pwrite64(dev_fd, &cmd, sizeof(cmd), + ret = pwrite(dev_fd, &cmd, sizeof(cmd), VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + PCI_COMMAND); @@ -194,7 +194,7 @@ pci_vfio_set_bus_master(int dev_fd, bool op) uint16_t reg; int ret; - ret = pread64(dev_fd, ®, sizeof(reg), + ret = pread(dev_fd, ®, sizeof(reg), VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + PCI_COMMAND); if (ret != sizeof(reg)) { @@ -208,7 +208,7 @@ pci_vfio_set_bus_master(int dev_fd, bool op) else reg &= ~(PCI_COMMAND_MASTER); - ret = pwrite64(dev_fd, ®, sizeof(reg), + ret = pwrite(dev_fd, ®, sizeof(reg), VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + PCI_COMMAND); @@ -464,7 +464,7 @@ pci_vfio_is_ioport_bar(int vfio_dev_fd, int bar_index) uint32_t ioport_bar; int ret; - ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar), + ret = pread(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar), VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + PCI_BASE_ADDRESS_0 + bar_index*4); if (ret != sizeof(ioport_bar)) { @@ -1133,7 +1133,7 @@ pci_vfio_ioport_read(struct rte_pci_ioport *p, if (vfio_dev_fd < 0) return; - if (pread64(vfio_dev_fd, data, + if (pread(vfio_dev_fd, data, len, p->base + offset) <= 0) RTE_LOG(ERR, EAL, "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n", @@ -1150,7 +1150,7 @@ pci_vfio_ioport_write(struct rte_pci_ioport *p, if (vfio_dev_fd < 0) return; - if (pwrite64(vfio_dev_fd, data, + if (pwrite(vfio_dev_fd, data, len, p->base + offset) <= 0) RTE_LOG(ERR, EAL, "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n", -- 2.39.2 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-06-25 00:22:13.380509740 +0100 +++ 0002-bus-pci-fix-build-with-musl-1.2.4-Alpine-3.19.patch 2024-06-25 00:22:13.057183040 +0100 @@ -1 +1 @@ -From 884f83ccf74b5364430d3b21c653d5f6e359e091 Mon Sep 17 00:00:00 2001 +From 502049c8b3e997a10a3e77ad87d714ec2df63235 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 884f83ccf74b5364430d3b21c653d5f6e359e091 ] + @@ -10 +11,0 @@ -Cc: stable@dpdk.org @@ -17,2 +18,2 @@ - drivers/bus/pci/linux/pci_vfio.c | 18 +++++++++--------- - 1 file changed, 9 insertions(+), 9 deletions(-) + drivers/bus/pci/linux/pci_vfio.c | 28 ++++++++++++++-------------- + 1 file changed, 14 insertions(+), 14 deletions(-) @@ -21 +22 @@ -index 87c16e6603..05b03a9667 100644 +index fe83e1a04e..44c132ae8a 100644 @@ -24,2 +25,2 @@ -@@ -80,7 +80,7 @@ pci_vfio_read_config(const struct rte_pci_device *dev, - if ((uint64_t)len + offs > size) +@@ -53,7 +53,7 @@ pci_vfio_read_config(const struct rte_intr_handle *intr_handle, + if (vfio_dev_fd < 0) @@ -28,2 +29,3 @@ -- return pread64(fd, buf, len, offset + offs); -+ return pread(fd, buf, len, offset + offs); +- return pread64(vfio_dev_fd, buf, len, ++ return pread(vfio_dev_fd, buf, len, + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs); @@ -32,3 +34,2 @@ - int -@@ -101,7 +101,7 @@ pci_vfio_write_config(const struct rte_pci_device *dev, - if ((uint64_t)len + offs > size) +@@ -66,7 +66,7 @@ pci_vfio_write_config(const struct rte_intr_handle *intr_handle, + if (vfio_dev_fd < 0) @@ -37,2 +38,3 @@ -- return pwrite64(fd, buf, len, offset + offs); -+ return pwrite(fd, buf, len, offset + offs); +- return pwrite64(vfio_dev_fd, buf, len, ++ return pwrite(vfio_dev_fd, buf, len, + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs); @@ -41,4 +43,2 @@ - /* get PCI BAR number where MSI-X interrupts are */ -@@ -155,7 +155,7 @@ pci_vfio_enable_bus_memory(struct rte_pci_device *dev, int dev_fd) - return -1; - } +@@ -80,7 +80,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table) + uint8_t cap_id, cap_offset; @@ -46,2 +46,50 @@ -- ret = pread64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); -+ ret = pread(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); + /* read PCI capability pointer from config space */ +- ret = pread64(fd, ®, sizeof(reg), ++ ret = pread(fd, ®, sizeof(reg), + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + + PCI_CAPABILITY_LIST); + if (ret != sizeof(reg)) { +@@ -95,7 +95,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table) + while (cap_offset) { + + /* read PCI capability ID */ +- ret = pread64(fd, ®, sizeof(reg), ++ ret = pread(fd, ®, sizeof(reg), + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + + cap_offset); + if (ret != sizeof(reg)) { +@@ -109,7 +109,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table) + + /* if we haven't reached MSI-X, check next capability */ + if (cap_id != PCI_CAP_ID_MSIX) { +- ret = pread64(fd, ®, sizeof(reg), ++ ret = pread(fd, ®, sizeof(reg), + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + + cap_offset); + if (ret != sizeof(reg)) { +@@ -126,7 +126,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table) + /* else, read table offset */ + else { + /* table offset resides in the next 4 bytes */ +- ret = pread64(fd, ®, sizeof(reg), ++ ret = pread(fd, ®, sizeof(reg), + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + + cap_offset + 4); + if (ret != sizeof(reg)) { +@@ -135,7 +135,7 @@ pci_vfio_get_msix_bar(int fd, struct pci_msix_table *msix_table) + return -1; + } + +- ret = pread64(fd, &flags, sizeof(flags), ++ ret = pread(fd, &flags, sizeof(flags), + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + + cap_offset + 2); + if (ret != sizeof(flags)) { +@@ -162,7 +162,7 @@ pci_vfio_enable_bus_memory(int dev_fd) + uint16_t cmd; + int ret; + +- ret = pread64(dev_fd, &cmd, sizeof(cmd), ++ ret = pread(dev_fd, &cmd, sizeof(cmd), + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + + PCI_COMMAND); @@ -49,3 +97 @@ - if (ret != sizeof(cmd)) { - RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n"); -@@ -166,7 +166,7 @@ pci_vfio_enable_bus_memory(struct rte_pci_device *dev, int dev_fd) +@@ -175,7 +175,7 @@ pci_vfio_enable_bus_memory(int dev_fd) @@ -54,9 +100,27 @@ - cmd |= RTE_PCI_COMMAND_MEMORY; -- ret = pwrite64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); -+ ret = pwrite(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); - - if (ret != sizeof(cmd)) { - RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n"); -@@ -425,7 +425,7 @@ pci_vfio_is_ioport_bar(const struct rte_pci_device *dev, int vfio_dev_fd, - return -1; - } + cmd |= PCI_COMMAND_MEMORY; +- ret = pwrite64(dev_fd, &cmd, sizeof(cmd), ++ ret = pwrite(dev_fd, &cmd, sizeof(cmd), + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + + PCI_COMMAND); + +@@ -194,7 +194,7 @@ pci_vfio_set_bus_master(int dev_fd, bool op) + uint16_t reg; + int ret; + +- ret = pread64(dev_fd, ®, sizeof(reg), ++ ret = pread(dev_fd, ®, sizeof(reg), + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + + PCI_COMMAND); + if (ret != sizeof(reg)) { +@@ -208,7 +208,7 @@ pci_vfio_set_bus_master(int dev_fd, bool op) + else + reg &= ~(PCI_COMMAND_MASTER); + +- ret = pwrite64(dev_fd, ®, sizeof(reg), ++ ret = pwrite(dev_fd, ®, sizeof(reg), + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + + PCI_COMMAND); + +@@ -464,7 +464,7 @@ pci_vfio_is_ioport_bar(int vfio_dev_fd, int bar_index) + uint32_t ioport_bar; + int ret; @@ -66 +130,2 @@ - offset + RTE_PCI_BASE_ADDRESS_0 + bar_index * 4); + VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + + PCI_BASE_ADDRESS_0 + bar_index*4); @@ -68,2 +133 @@ - RTE_LOG(ERR, EAL, "Cannot read command (%x) from config space!\n", -@@ -1276,7 +1276,7 @@ pci_vfio_ioport_read(struct rte_pci_ioport *p, +@@ -1133,7 +1133,7 @@ pci_vfio_ioport_read(struct rte_pci_ioport *p, @@ -78 +142 @@ -@@ -1293,7 +1293,7 @@ pci_vfio_ioport_write(struct rte_pci_ioport *p, +@@ -1150,7 +1150,7 @@ pci_vfio_ioport_write(struct rte_pci_ioport *p, @@ -87,18 +150,0 @@ -@@ -1324,7 +1324,7 @@ pci_vfio_mmio_read(const struct rte_pci_device *dev, int bar, - if ((uint64_t)len + offs > size) - return -1; - -- return pread64(fd, buf, len, offset + offs); -+ return pread(fd, buf, len, offset + offs); - } - - int -@@ -1344,7 +1344,7 @@ pci_vfio_mmio_write(const struct rte_pci_device *dev, int bar, - if ((uint64_t)len + offs > size) - return -1; - -- return pwrite64(fd, buf, len, offset + offs); -+ return pwrite(fd, buf, len, offset + offs); - } - - int