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Sun, 7 Jul 2024 03:25:55 -0700 From: Itamar Gozlan To: , , , , , , , , Dariusz Sosnowski , Bing Zhao , Ori Kam , Matan Azrad CC: , Subject: [PATCH 05/10] net/mlx5/hws: strictly range templates check fix Date: Sun, 7 Jul 2024 13:25:26 +0300 Message-ID: <20240707102532.2045942-5-igozlan@nvidia.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240707102532.2045942-1-igozlan@nvidia.com> References: <20240707102532.2045942-1-igozlan@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4C:EE_|LV2PR12MB5943:EE_ X-MS-Office365-Filtering-Correlation-Id: e0f9abe8-5b62-4ade-aa6e-08dc9e6f32fd X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|1800799024|82310400026|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?JD+arQ54pZeBQt/v4Q6LLWQHkdfoq4yD5VTYvOxHxZkXNfogMA6qFnuZVnCE?= =?us-ascii?Q?L1+UQhQbFeVd4YqQHL1EkkMSdGhhSKuHlVSR1/5Onge0F8uVweb1rzWq1WfW?= =?us-ascii?Q?u0ZAPdV8VSHG7ObvEAQk0Per4sdyMsLTZlrZzOvSIa/ntCM77UlzeN6OJa/x?= =?us-ascii?Q?9dOi8XwNLIDf4ywSvwC3vhyc4iQlrJIDcwSvW6bNJqY4Mb5nLx1rF+02m2+g?= =?us-ascii?Q?VZlijKc+UqclBmmLwunLoxbrN7oKAyJnT1hx0KRINdTeWYneT4rB9pQl5WFH?= =?us-ascii?Q?GU3RnvhI2s+NuNgZvgkSpo2VhPH1Ek2bkIyWOAIIt4wSNRlcV/pqbSogFjhp?= =?us-ascii?Q?f874Gv0Xfuox45o5nR1iBRb+3YE6udq4P1vzG+uUEGMCSuiM6HD8yil4NWtp?= =?us-ascii?Q?nMHNo46hwhsCchbrkbtcgKYtWEbiAvcRCLg9hB+aPX5ZCayLZyLx5WDN4oy/?= =?us-ascii?Q?Ek5kX/q4/fplw64b0+rRegZIrNRQzrMKKheEUEOdcrLFueJFe8cAv5ElU0k2?= =?us-ascii?Q?FI7l3Rp3z1jaHnFM+4B4DJSkTHm3a8W+Mui688AXsey88xVAWtEbmptDm2xh?= =?us-ascii?Q?Qfx2iF7lSdrU3AIcy4fEc+UxACzLDuLuLxQ683GAbeBFtbs2SO/m0wFPKEZM?= =?us-ascii?Q?zrLCQEvjGsUUvS2FCd+eDpmudkK8qJHB8S4zUnjrlFp4Q09DpmDvxqhFsBfk?= =?us-ascii?Q?l2UjqYjJw1T+YXVv7SGaRjwosvwvl7RFkqgZRcgVRAw43dTXnBka7MRS7yrs?= =?us-ascii?Q?NDOd6GWBOFCTvWYdzkxkBzyi+VSyDdBwZSO2d3XLht5Tc01WdJiYP0qfKlVS?= =?us-ascii?Q?5997olp2+CC6SB6k2lIZ1lQLEj25DrOKkEN/Y0o8vRLlJpUzFqznXYyqR9LJ?= =?us-ascii?Q?DzbLPkn+YgPdfMOVzTHAuz3XR7GMPTY3IHnbx7aeDHPsqDpSpkehRI/GxJ07?= =?us-ascii?Q?HAsSNu6P88YTaGIdGwenlOTkOHHNvgHnMxkamdrYzxhZFcc0QgqzHmlI42Qh?= =?us-ascii?Q?6wtJLdF6cTFF4jfEGG2C0RYD1HiPGRG4n99lBW7zJWn9OvRdMhf2OO3fnCsK?= =?us-ascii?Q?qOZhJ2vyo34klMX9RU+fZSnJ1HOp8jKgFux/QzTal4O4dO3FCWf3854TgLDq?= =?us-ascii?Q?XMm5S58yHHDh4R1Dp+qbFGvf8jUxsw9uel+UQaEo1871LOIJa4g2U0JnwNLL?= =?us-ascii?Q?EZTKV76wQx6BjMitDBSXu5x3RiM+SihbUAP4GtcdpSzwo4Wcn3QsRIAvp7+A?= =?us-ascii?Q?xq6cyZqxqQaUHKh7kv6ceN40ql1N8uC5v2fZFSsGy7x3wQlcGn+6yquEVSty?= =?us-ascii?Q?MJhVhl1JSUEV4YUyBDEmxsnJCUFFVGaBr30fl1aZEZZ9Vm5GhUbQduUGHc9/?= =?us-ascii?Q?4hH7lSF5SKgijNKmLM0O8K3p3iuMy8Rp3HZ2XSeB1N3kvFICr0Uxau7Sm+pB?= =?us-ascii?Q?EFe8Ekc+6mSbNrOs6xDj/oxWns5t6XkIjgUC+soRTtmI8TTD7AAc2Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jul 2024 10:26:01.2561 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0f9abe8-5b62-4ade-aa6e-08dc9e6f32fd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5943 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Using range and non range templates is not allowed, and in HWS there is a check that enforce that limitation with constantly check that, in a loop, if the current template defined as range, the last one should also be defined as range. But, in the case where there are two templates in the following order: (1) template with range, and (2) template without range. The existing checks will not cover this case. This commit fixes that hole by maintain the invariant that if a template without a range exist, all the previous match template are also. Fixes: 9732ffe13bd6 ("net/mlx5/hws: add range definer creation") Cc: valex@nvidia.com Cc: stable@dpdk.org Signed-off-by: Itamar Gozlan Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_definer.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 9ebda9267d..51a3f7be4b 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -4041,15 +4041,18 @@ mlx5dr_definer_matcher_range_init(struct mlx5dr_context *ctx, /* Create optional range definers */ for (i = 0; i < matcher->num_of_mt; i++) { - if (!mt[i].fcr_sz) - continue; - /* All must use range if requested */ - if (i && !mt[i - 1].range_definer) { + bool is_range = !!mt[i].fcr_sz; + bool has_range = matcher->flags & MLX5DR_MATCHER_FLAGS_RANGE_DEFINER; + + if (i && ((is_range && !has_range) || (!is_range && has_range))) { DR_LOG(ERR, "Using range and non range templates is not allowed"); goto free_definers; } + if (!mt[i].fcr_sz) + continue; + matcher->flags |= MLX5DR_MATCHER_FLAGS_RANGE_DEFINER; /* Create definer without fcr binding, already binded */ mt[i].range_definer = mlx5dr_definer_alloc(ctx, -- 2.39.3