From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <stable-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id 6D41C45610
for <public@inbox.dpdk.org>; Fri, 12 Jul 2024 12:48:37 +0200 (CEST)
Received: from mails.dpdk.org (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id 661B8402E5;
Fri, 12 Jul 2024 12:48:37 +0200 (CEST)
Received: from NAM02-SN1-obe.outbound.protection.outlook.com
(mail-sn1nam02on2053.outbound.protection.outlook.com [40.107.96.53])
by mails.dpdk.org (Postfix) with ESMTP id 6ED1040261
for <stable@dpdk.org>; Fri, 12 Jul 2024 12:48:35 +0200 (CEST)
ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;
b=pKWevmr/MwJ71YPyJfB7wVCNha7muRP4/J3u7UmZKk/jKexkK8cfQaIu1F5UFjkJR7q5WW/GaJG2XysONjlWnMWmnRrLZe6bdZiNNLgHDgGuJooQv/pbhqUh7dkMn35Ui60iUw+EtTBRvNXhZ+6NbvugXHsf+fN7u4fbZ/hBbZcgcooqa4KiuIEEnu8P/xBVMkSYNkfhUrqGZ00qtaJd3TczFrGv6U1GOIlEZstgX3STC8t4NkVomBT0aswP43YANH2py3hZ9wBc4vSq411g2Hj1gEyDoDCqinbq3m442xkuDRqyREegtAJ0SJlWbWeV/rCgZn3bZ9E0eoq/r6foIA==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;
s=arcselector10001;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;
bh=p4GWFyJ+pH2nagFMqz2mmMltzAmeKRHOpeGtOllvxvQ=;
b=t4AwzxWAy8T65s8G4jV5kHsdFdZlsZHtVmFQ9fgl3uI4BkPOZl/ziTgh7Eqz2EkpoXV6KxGyIMtoeQ58ZeZbKjIYwecbf85uFXlcLVixaLwyWahs2VtGTRbRgp6T7gA3Mh6bU6TilKf//UTOsDYIh6RED/uy/9DxMSQd9qWg4HAsrJvdfRDy4V4YqscQx/sJw3UsWg8BnZdC1Vgebgpq0A/EeKV9U2uARWsIAacn7giQiszT2aeHbMHq56Y/xu1V7zD0AwV729mtKDPzIMR/MDAa5NfAo03cs8nMJf1IC8k+ISaskl0VItSVrlB0I6dhV/VereuCavL6/BvvC3jsRQ==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is
216.228.117.161) smtp.rcpttodomain=corigine.com smtp.mailfrom=nvidia.com;
dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;
dkim=none (message not signed); arc=none (0)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;
s=selector2;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
bh=p4GWFyJ+pH2nagFMqz2mmMltzAmeKRHOpeGtOllvxvQ=;
b=c1veNfsf7E09TfOu8+ADMBT9LWiKPbQa49jKl9gSZoKUbqu+rvROErADaudMDgI1UWANLovJMB9psBb5Kv6CGYFM5gL+V4V1sHWjJKuh2Z6UdneYqlDvOguf0Xgj5kB/nKKlMz05eYsBF0MYcpyE4n/G96Q4mexuh7MWlk0QS4O21XzNIWfJitqxTAIe9t8CnQsCmlGmERkefzUUy9E8PRomYJjSC+rupfQWe7ANkW42T7chU1I8fWbLoZFTGLh7llTZ9GFhrtG8y7mcv0MrmRbHQK9HCmOGeRKUW0Y1PkPkTyLCsXmgZmfOVkuiliLV+8X5oqLaXbl8cTN1VmgjAA==
Received: from DS7PR03CA0039.namprd03.prod.outlook.com (2603:10b6:5:3b5::14)
by PH0PR12MB7862.namprd12.prod.outlook.com (2603:10b6:510:26d::9) with
Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7741.35; Fri, 12 Jul
2024 10:48:30 +0000
Received: from DS1PEPF0001709A.namprd05.prod.outlook.com
(2603:10b6:5:3b5:cafe::ec) by DS7PR03CA0039.outlook.office365.com
(2603:10b6:5:3b5::14) with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7762.23 via Frontend
Transport; Fri, 12 Jul 2024 10:48:30 +0000
X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161)
smtp.mailfrom=nvidia.com;
dkim=none (message not signed)
header.d=none;dmarc=pass action=none header.from=nvidia.com;
Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates
216.228.117.161 as permitted sender) receiver=protection.outlook.com;
client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C
Received: from mail.nvidia.com (216.228.117.161) by
DS1PEPF0001709A.mail.protection.outlook.com (10.167.18.104) with Microsoft
SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id
15.20.7762.17 via Frontend Transport; Fri, 12 Jul 2024 10:48:30 +0000
Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com
(10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 12 Jul
2024 03:48:18 -0700
Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com
(10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 12 Jul
2024 03:48:15 -0700
From: Xueming Li <xuemingl@nvidia.com>
To: Chaoyong He <chaoyong.he@corigine.com>
CC: Long Wu <long.wu@corigine.com>, Peng Zhang <peng.zhang@corigine.com>,
"dpdk stable" <stable@dpdk.org>
Subject: patch 'net/nfp: fix configuration BAR' has been queued to stable
release 23.11.2
Date: Fri, 12 Jul 2024 18:44:13 +0800
Message-ID: <20240712104528.308638-28-xuemingl@nvidia.com>
X-Mailer: git-send-email 2.34.1
In-Reply-To: <20240712104528.308638-1-xuemingl@nvidia.com>
References: <20240712104528.308638-1-xuemingl@nvidia.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-Originating-IP: [10.126.231.35]
X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To
rnnvmail201.nvidia.com (10.129.68.8)
X-EOPAttributedMessage: 0
X-MS-PublicTrafficType: Email
X-MS-TrafficTypeDiagnostic: DS1PEPF0001709A:EE_|PH0PR12MB7862:EE_
X-MS-Office365-Filtering-Correlation-Id: dd530c7f-4716-4a8b-63fa-08dca2602b0c
X-MS-Exchange-SenderADCheck: 1
X-MS-Exchange-AntiSpam-Relay: 0
X-Microsoft-Antispam: BCL:0;
ARA:13230040|82310400026|1800799024|36860700013|376014;
X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ou4dgddyxklRXU3aClpNZVmrPDJdWWCjWu+yI10AyXDYFA7U1gJIVxuHCoMf?=
=?us-ascii?Q?xQgKdFSS7EgB2dD/mtZ3f0OqA4P6c1cQGnQUUJ56A1EdWIAJnbOl4qoTstbR?=
=?us-ascii?Q?x4bhHayVUSbwfhU9vZejtU17qs5T3MUEBc1+O9PmZzQjYZRhjeLx4xOAbuHU?=
=?us-ascii?Q?0y23yBd0YmRg+fAc242UCtSYPPQYQ13Z+BX6BOyInesnIFbRuKrL7wIHMium?=
=?us-ascii?Q?Qs5dmSFjd5HUCXtp28LMa37OSx6QOAGH9KzRsPVOr9N3LlV8NUKUTPpCBRue?=
=?us-ascii?Q?vqMMpgNQ0/rOQdtyj5fGmu7umfgc9Y41WhYv4EWSiJvYEC8MIQgfwg3nCIJp?=
=?us-ascii?Q?81Pqa6jQ4sveDSsR/bH5AVK8Ez7OMRuQQCefTdNxGBmJEcKf0Ym/Pap2CMpw?=
=?us-ascii?Q?sndNTiIBRT3NFovdxIRi2eHfuN3PmLfdDS1NLiBpAYPtT9tnhyKRk6eCNSSt?=
=?us-ascii?Q?7InjReiGz7kW+roAxFyMvU4y9nsxI8rd4VxZNrtN7ZDKU4yqZQ89Z07chqK6?=
=?us-ascii?Q?TtgOB6G+kqVOB2Zcv2CJ2e0S5Nb8mW8flGip57NHb/72mpzartfYYBs7dbdL?=
=?us-ascii?Q?FXIC95DxjySNcFcoLH2AsrYQ3GO88oO2yNO59LVLXwcL3GwU90/yPVddaf6w?=
=?us-ascii?Q?M+F74eexAtcEvubQUWUpP/xn0fwMF68t1JC3vM7JJRbW/40UXCJopEtzIqmC?=
=?us-ascii?Q?X/oNVeNcwPC1869PEk7SYG+cCuPHInTH245CarZNBa+NvY+nQRfFHkTiBazt?=
=?us-ascii?Q?cxIoVLetRQRopgXm9x3Bg3Rmc/+N3cXmHdO42IRuKyVdPu37WVi4d+lzpy6H?=
=?us-ascii?Q?Mqe12MJIXEcupxtej67oowyAnmTNGiofxBB3FOTaRb4/SvjP89B30s8zMy9f?=
=?us-ascii?Q?BPg39PtTjYhVuEvbEMRdCI6t2R4k7hqmZ6OEHO7NnhW9TTUhKjgMBBhUaAPF?=
=?us-ascii?Q?oHZ4sezJqkzncEGLPY/GiXxAPwyBRzCKBnuBJZCYQRHWt6HalinCH7RojLi3?=
=?us-ascii?Q?6nOK/dJPboM/iMy811iZvU2uRDKwu4Iug4/720hqAGaDlHlaYdZnQ5H6k66A?=
=?us-ascii?Q?5YFgzasf6RUbX1fGZzVbR2E23mTTan82fdigxwEFdS/Z2eN7pUEwfeQMs0os?=
=?us-ascii?Q?jeFOTpzYCMqXB1ri3BCNtp16Bc+ShzhXGsa0M3lF4d4Suf+T1ItsMZfdWAhC?=
=?us-ascii?Q?VuXJkR2w7mvTmPfDTHQ4NjPt4awqAeYN46RTpmACAFAsVMmvV6rcUpSAN+xF?=
=?us-ascii?Q?fCDPFUhrilU/0xUolDvEeGCh3tw54ozDDBEuMXyBeRTnqec59wFrDKzN+9gm?=
=?us-ascii?Q?y4bkUDn76qSw6IpTOFjLev2S+x1RH6qhhCR/XEZuDlgi8nQ3/a8+dJvRayT8?=
=?us-ascii?Q?bZZtocvfHAV6ciUc8wxELnHJvafF4DWX/ydmJYZIjeUdxGVdoQciokAcAiya?=
=?us-ascii?Q?92Vgx2zZewj8VjZLCKQ531c7P3o4WBbr?=
X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:;
IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;
SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014); DIR:OUT;
SFP:1101;
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2024 10:48:30.0841 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: dd530c7f-4716-4a8b-63fa-08dca2602b0c
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];
Helo=[mail.nvidia.com]
X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709A.namprd05.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7862
X-BeenThere: stable@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: patches for DPDK stable branches <stable.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/stable>,
<mailto:stable-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/stable/>
List-Post: <mailto:stable@dpdk.org>
List-Help: <mailto:stable-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/stable>,
<mailto:stable-request@dpdk.org?subject=subscribe>
Errors-To: stable-bounces@dpdk.org
Hi,
FYI, your patch has been queued to stable release 23.11.2
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/14/24. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging
This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=a683a82c9836e74b15bbaeca69d72807575b30d0
Thanks.
Xueming Li <xuemingl@nvidia.com>
---
>From a683a82c9836e74b15bbaeca69d72807575b30d0 Mon Sep 17 00:00:00 2001
From: Chaoyong He <chaoyong.he@corigine.com>
Date: Fri, 19 Apr 2024 13:23:43 +0800
Subject: [PATCH] net/nfp: fix configuration BAR
Cc: Xueming Li <xuemingl@nvidia.com>
[ upstream commit debb9e735adb1bccb2f75ee1372ea2e6c6b20673 ]
All the configuration bars are sit in an array, and the initial logic
sort all the configuration BAR from small to large based on size and
index, which result all valid bars are behind the invalid bars.
But the BAR alloc logic search this array from the very beginning and
only try limited times (equal to the valid bars number).
It's ok for primary process because which has enough valid bars, and
finally it can find one to use.
But for secondary process and run with igb_uio driver, the valid bars
are very limit, and it can not find one, and the logic will fail.
Fix this by drop the sort logic, and search the bar array from the end
to begin.
Fixes: 1fbe51cd9c3a ("net/nfp: extend usage of BAR from 8 to 24")
Signed-off-by: Chaoyong He <chaoyong.he@corigine.com>
Reviewed-by: Long Wu <long.wu@corigine.com>
Reviewed-by: Peng Zhang <peng.zhang@corigine.com>
---
drivers/net/nfp/nfpcore/nfp6000_pcie.c | 34 +++++++++-----------------
1 file changed, 11 insertions(+), 23 deletions(-)
diff --git a/drivers/net/nfp/nfpcore/nfp6000_pcie.c b/drivers/net/nfp/nfpcore/nfp6000_pcie.c
index a6fd89b6c8..ef1ffd6d01 100644
--- a/drivers/net/nfp/nfpcore/nfp6000_pcie.c
+++ b/drivers/net/nfp/nfpcore/nfp6000_pcie.c
@@ -263,19 +263,6 @@ nfp_bitsize_calc(uint64_t mask)
return bit_size;
}
-static int
-nfp_cmp_bars(const void *ptr_a,
- const void *ptr_b)
-{
- const struct nfp_bar *a = ptr_a;
- const struct nfp_bar *b = ptr_b;
-
- if (a->bitsize == b->bitsize)
- return a->index - b->index;
- else
- return a->bitsize - b->bitsize;
-}
-
static bool
nfp_bars_for_secondary(uint32_t index)
{
@@ -383,9 +370,6 @@ nfp_enable_bars(struct nfp_pcie_user *nfp)
if (nfp_bar_write(nfp, bar, barcfg_msix_general) < 0)
return -EIO;
- /* Sort bars by bit size - use the smallest possible first. */
- qsort(&nfp->bar[0], nfp->bars, sizeof(nfp->bar[0]), nfp_cmp_bars);
-
return 0;
}
@@ -466,16 +450,18 @@ find_matching_bar(struct nfp_pcie_user *nfp,
int width)
{
uint32_t n;
+ uint32_t index;
- for (n = 0; n < nfp->bars; n++) {
- struct nfp_bar *bar = &nfp->bar[n];
+ for (n = RTE_DIM(nfp->bar) ; n > 0; n--) {
+ index = n - 1;
+ struct nfp_bar *bar = &nfp->bar[index];
if (bar->lock)
continue;
if (matching_bar_exist(bar, target, action, token,
offset, size, width))
- return n;
+ return index;
}
return -1;
@@ -493,10 +479,12 @@ find_unused_bar_noblock(struct nfp_pcie_user *nfp,
{
int ret;
uint32_t n;
+ uint32_t index;
const struct nfp_bar *bar;
- for (n = 0; n < nfp->bars; n++) {
- bar = &nfp->bar[n];
+ for (n = RTE_DIM(nfp->bar); n > 0; n--) {
+ index = n - 1;
+ bar = &nfp->bar[index];
if (bar->bitsize == 0)
continue;
@@ -508,7 +496,7 @@ find_unused_bar_noblock(struct nfp_pcie_user *nfp,
continue;
if (!bar->lock)
- return n;
+ return index;
}
return -EAGAIN;
@@ -561,7 +549,7 @@ nfp_disable_bars(struct nfp_pcie_user *nfp)
uint32_t i;
struct nfp_bar *bar;
- for (i = 0; i < nfp->bars; i++) {
+ for (i = 0; i < RTE_DIM(nfp->bar); i++) {
bar = &nfp->bar[i];
if (bar->iomem != NULL) {
bar->iomem = NULL;
--
2.34.1
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2024-07-12 18:40:15.468468363 +0800
+++ 0027-net-nfp-fix-configuration-BAR.patch 2024-07-12 18:40:13.986594241 +0800
@@ -1 +1 @@
-From debb9e735adb1bccb2f75ee1372ea2e6c6b20673 Mon Sep 17 00:00:00 2001
+From a683a82c9836e74b15bbaeca69d72807575b30d0 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl@nvidia.com>
+
+[ upstream commit debb9e735adb1bccb2f75ee1372ea2e6c6b20673 ]
@@ -21 +23,0 @@
-Cc: stable@dpdk.org