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From: Xueming Li <xuemingl@nvidia.com>
To: Venkat Kumar Ande <venkatkumar.ande@amd.com>
CC: Selwin Sebastian <selwin.sebastian@amd.com>, dpdk stable <stable@dpdk.org>
Subject: patch 'net/axgbe: enable PLL control for fixed PHY modes only' has
been queued to stable release 23.11.2
Date: Fri, 12 Jul 2024 18:44:21 +0800
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Errors-To: stable-bounces@dpdk.org
Hi,
FYI, your patch has been queued to stable release 23.11.2
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 07/14/24. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.
Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging
This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=92bc6bd0717bbb501a36721ade61da430c40c5ad
Thanks.
Xueming Li <xuemingl@nvidia.com>
---
>From 92bc6bd0717bbb501a36721ade61da430c40c5ad Mon Sep 17 00:00:00 2001
From: Venkat Kumar Ande <venkatkumar.ande@amd.com>
Date: Tue, 4 Jun 2024 17:41:39 +0530
Subject: [PATCH] net/axgbe: enable PLL control for fixed PHY modes only
Cc: Xueming Li <xuemingl@nvidia.com>
[ upstream commit 1c68b393b8ba05b6ddb321e3632d45fc1021ed96 ]
PLL control setting is needed only in fixed PHY configuration to
fix the peer-peer issues. Without the PLL control setting, the link up
takes longer time in a fixed PHY configuration.
Without the fix the user will not get the link come UP.
Driver implements SW RRC for Autoneg On configuration, hence PLL control
setting is not needed for AN On configuration, and can be skipped.
Also, PLL re-initialization is not needed for PHY Power Off and RRC
commands. Otherwise, they lead to mailbox errors. Added the changes
accordingly.
Fixes: 09b0a36cc7ae ("net/axgbe: toggle PLL settings during rate change")
Signed-off-by: Venkat Kumar Ande <venkatkumar.ande@amd.com>
Acked-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_phy_impl.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index 46ee5f0617..040176b8ef 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1228,6 +1228,10 @@ static void axgbe_phy_rx_reset(struct axgbe_port *pdata)
static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
{
+ /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */
+ if (pdata->phy.autoneg != AUTONEG_DISABLE)
+ return;
+
XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
XGBE_PMA_PLL_CTRL_MASK,
enable ? XGBE_PMA_PLL_CTRL_SET
@@ -1272,8 +1276,9 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
axgbe_phy_rx_reset(pdata);
reenable_pll:
- /* Re-enable the PLL control */
- axgbe_phy_pll_ctrl(pdata, true);
+ /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */
+ if (cmd != 0 && cmd != 5)
+ axgbe_phy_pll_ctrl(pdata, true);
PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
}
--
2.34.1
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2024-07-12 18:40:15.773762827 +0800
+++ 0035-net-axgbe-enable-PLL-control-for-fixed-PHY-modes-onl.patch 2024-07-12 18:40:14.006594239 +0800
@@ -1 +1 @@
-From 1c68b393b8ba05b6ddb321e3632d45fc1021ed96 Mon Sep 17 00:00:00 2001
+From 92bc6bd0717bbb501a36721ade61da430c40c5ad Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl@nvidia.com>
+
+[ upstream commit 1c68b393b8ba05b6ddb321e3632d45fc1021ed96 ]
@@ -20 +22,0 @@
-Cc: stable@dpdk.org
@@ -29 +31 @@
-index f51830f800..bcefbf28f2 100644
+index 46ee5f0617..040176b8ef 100644