From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F382F4569C for ; Wed, 24 Jul 2024 13:33:25 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D670E4334C; Wed, 24 Jul 2024 13:33:24 +0200 (CEST) Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mails.dpdk.org (Postfix) with ESMTP id F1F1442EFD for ; Wed, 24 Jul 2024 13:33:23 +0200 (CEST) Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4257d5fc9b7so58314985e9.2 for ; Wed, 24 Jul 2024 04:33:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1721820803; x=1722425603; darn=dpdk.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vGjHRRYwa2qzohVIvpifbR06NOTDXOWwmXX0FukWgdE=; b=E3VFCZDBdJ8GUYRLvgVhqZ0A4zCtsxZ8PR6L55moAX8JTyn9yWNytItX4+Vs7xpRHz lmecvY92sLd5kO1w0A8oCBKbzWZEkwtgD0wlIU/c1I7li2fHCoeX5y1czDDrTDWjnpJw uHgxL6KdHr804TcNbASPwAzfvcZQX4hiRDLvCQ4wHJKs8gOLS/cqpFaYa8TOsTu6zQ8S P+LWIFDC8jOLkO1mu+bV2xCgCs4dignOz9mOe/vtQfIozO7LBUgj3RLlvNHCZLtkV9AZ U0TbmA+/HRtvvUfSwo+oL3ux+ji6uXrxh5qMLbtT3Uh8SmyszlZPVi3ZKkdcb1SB6Iwc s6XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721820803; x=1722425603; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vGjHRRYwa2qzohVIvpifbR06NOTDXOWwmXX0FukWgdE=; b=RmTg1Ewol588fIsvc3+y+vwNEdIy4W/mlIwlOrhKFLgnM68UsS8DHIw9OdLsUVzJk+ f9ChWBFBu5bIMIDW7ZPpb4JTviouBIcH4t7STSFSL2O1QpkCp5QUxgXNjtipv/8A5V7r XQmnC5+7L8rariejFGfeUF0Vyy7ZdU5jk9U2VuPFER26p+OQr0n98ctKR+PcOJ0H8bu9 hs/bdP1ZG0VD0MLweeANjLeG+zfaDirvAcp/udkQiz6A/GhCiEFJMU8j2NX1eQIqLQM0 TRSiSgIwZtmXhNw+UPNDwsqBnH4Orx4SjhtlZqeBDW3bHBPLHcdD1+WWhBTdTt4B/BW6 /VOQ== X-Forwarded-Encrypted: i=1; AJvYcCVJ1qH7hy9/a3MPltet9gcdneq4DD84jpc1MEZAISy3iirX5k7AI7xE0oGUyeS52kkNsLt/r1/Y2WhLMznmsrw= X-Gm-Message-State: AOJu0YwAfCoAqjHJXd887n+qZsi5jTZo3Km0l1A+0ZbX8xJG5vWMrb7L G+8Cy7IYwTTQNchngJ8mKrjBSEnQL1kp0IS/ZB1CtqPCcibhJ5jvNwcJ0eZg X-Google-Smtp-Source: AGHT+IGQKxlFLxbfaNUP0cnCvGB3jqgLBPhZmRzhkGAkDq4oL1Md1RonndkRPQXyVtVApp+NdIRlUA== X-Received: by 2002:a05:600c:1c1c:b0:426:5520:b835 with SMTP id 5b1f17b1804b1-427f7ab64d4mr22713785e9.5.1721820803076; Wed, 24 Jul 2024 04:33:23 -0700 (PDT) Received: from localhost ([2a01:4b00:d036:ae00:7aef:1aaa:3dff:d546]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-427f939aafdsm24667315e9.28.2024.07.24.04.33.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jul 2024 04:33:22 -0700 (PDT) From: luca.boccassi@gmail.com To: Brian Dooley Cc: Arkadiusz Kusztal , dpdk stable Subject: patch 'crypto/qat: fix GEN4 write' has been queued to stable release 22.11.6 Date: Wed, 24 Jul 2024 12:32:39 +0100 Message-Id: <20240724113318.616754-1-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240715152704.2229503-86-luca.boccassi@gmail.com> References: <20240715152704.2229503-86-luca.boccassi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 07/26/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/bluca/dpdk-stable This queued commit can be viewed at: https://github.com/bluca/dpdk-stable/commit/e793a7063f95d32916301282a820ffb16933b25e Thanks. Luca Boccassi --- >From e793a7063f95d32916301282a820ffb16933b25e Mon Sep 17 00:00:00 2001 From: Brian Dooley Date: Fri, 12 Jul 2024 15:48:51 +0100 Subject: [PATCH] crypto/qat: fix GEN4 write [ upstream commit c355c2d8e65f02fa9621249c9b2a111477230c89 ] All generations of QAT use the same Gen1 raw datapath. Gen4 needs a different WRITE function than other generations. Added separation for configuration of raw ctx for Gen4 from the Gen1 codepath. Fixes: 85fec6fd9674 ("crypto/qat: unify raw data path functions") Signed-off-by: Brian Dooley Acked-by: Arkadiusz Kusztal --- drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 121 ++++++++++++++++++- drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 6 + 2 files changed, 123 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index b219a418ba..52218e5a0a 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -9,6 +9,7 @@ #include "qat_asym.h" #include "qat_crypto.h" #include "qat_crypto_pmd_gens.h" +#include "adf_transport_access_macros_gen4vf.h" static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = { QAT_SYM_CIPHER_CAP(AES_CBC, @@ -223,6 +224,78 @@ qat_sym_build_op_aead_gen4(void *in_op, struct qat_sym_session *ctx, return 0; } +int +qat_sym_dp_enqueue_done_gen4(void *qp_data, uint8_t *drv_ctx, uint32_t n) +{ + struct qat_qp *qp = qp_data; + struct qat_queue *tx_queue = &qp->tx_q; + struct qat_sym_dp_ctx *dp_ctx = (void *)drv_ctx; + + if (unlikely(dp_ctx->cached_enqueue != n)) + return -1; + + qp->enqueued += n; + qp->stats.enqueued_count += n; + + tx_queue->tail = dp_ctx->tail; + + WRITE_CSR_RING_TAIL_GEN4VF(qp->mmap_bar_addr, + tx_queue->hw_bundle_number, + tx_queue->hw_queue_number, tx_queue->tail); + + tx_queue->csr_tail = tx_queue->tail; + dp_ctx->cached_enqueue = 0; + + return 0; +} + +int +qat_sym_dp_dequeue_done_gen4(void *qp_data, uint8_t *drv_ctx, uint32_t n) +{ + struct qat_qp *qp = qp_data; + struct qat_queue *rx_queue = &qp->rx_q; + struct qat_sym_dp_ctx *dp_ctx = (void *)drv_ctx; + + if (unlikely(dp_ctx->cached_dequeue != n)) + return -1; + + rx_queue->head = dp_ctx->head; + rx_queue->nb_processed_responses += n; + qp->dequeued += n; + qp->stats.dequeued_count += n; + if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH) { + uint32_t old_head, new_head; + uint32_t max_head; + + old_head = rx_queue->csr_head; + new_head = rx_queue->head; + max_head = qp->nb_descriptors * rx_queue->msg_size; + + /* write out free descriptors */ + void *cur_desc = (uint8_t *)rx_queue->base_addr + old_head; + + if (new_head < old_head) { + memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, + max_head - old_head); + memset(rx_queue->base_addr, ADF_RING_EMPTY_SIG_BYTE, + new_head); + } else { + memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - + old_head); + } + rx_queue->nb_processed_responses = 0; + rx_queue->csr_head = new_head; + + /* write current head to CSR */ + WRITE_CSR_RING_HEAD_GEN4VF(qp->mmap_bar_addr, + rx_queue->hw_bundle_number, rx_queue->hw_queue_number, + new_head); + } + + dp_ctx->cached_dequeue = 0; + return 0; +} + static int qat_sym_crypto_set_session_gen4(void *cdev, void *session) { @@ -383,11 +456,51 @@ qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void *_ctx) { struct rte_crypto_raw_dp_ctx *raw_dp_ctx = _raw_dp_ctx; struct qat_sym_session *ctx = _ctx; - int ret; - ret = qat_sym_configure_raw_dp_ctx_gen1(_raw_dp_ctx, _ctx); - if (ret < 0) - return ret; + raw_dp_ctx->enqueue_done = qat_sym_dp_enqueue_done_gen4; + raw_dp_ctx->dequeue_burst = qat_sym_dp_dequeue_burst_gen1; + raw_dp_ctx->dequeue = qat_sym_dp_dequeue_single_gen1; + raw_dp_ctx->dequeue_done = qat_sym_dp_dequeue_done_gen4; + + if ((ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER || + ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) && + !ctx->is_gmac) { + /* AES-GCM or AES-CCM */ + if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 || + ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 || + (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128 + && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE + && ctx->qat_hash_alg == + ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) { + raw_dp_ctx->enqueue_burst = + qat_sym_dp_enqueue_aead_jobs_gen1; + raw_dp_ctx->enqueue = + qat_sym_dp_enqueue_single_aead_gen1; + } else { + raw_dp_ctx->enqueue_burst = + qat_sym_dp_enqueue_chain_jobs_gen1; + raw_dp_ctx->enqueue = + qat_sym_dp_enqueue_single_chain_gen1; + } + } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH || ctx->is_gmac) { + raw_dp_ctx->enqueue_burst = qat_sym_dp_enqueue_auth_jobs_gen1; + raw_dp_ctx->enqueue = qat_sym_dp_enqueue_single_auth_gen1; + } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) { + if (ctx->qat_mode == ICP_QAT_HW_CIPHER_AEAD_MODE || + ctx->qat_cipher_alg == + ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305) { + raw_dp_ctx->enqueue_burst = + qat_sym_dp_enqueue_aead_jobs_gen1; + raw_dp_ctx->enqueue = + qat_sym_dp_enqueue_single_aead_gen1; + } else { + raw_dp_ctx->enqueue_burst = + qat_sym_dp_enqueue_cipher_jobs_gen1; + raw_dp_ctx->enqueue = + qat_sym_dp_enqueue_single_cipher_gen1; + } + } else + return -1; if (ctx->is_single_pass && ctx->is_ucs) { raw_dp_ctx->enqueue_burst = qat_sym_dp_enqueue_aead_jobs_gen4; diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h index 2b1b0eb717..1acb0c4985 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h @@ -927,6 +927,12 @@ qat_sym_dp_enqueue_done_gen1(void *qp_data, uint8_t *drv_ctx, uint32_t n); int qat_sym_dp_dequeue_done_gen1(void *qp_data, uint8_t *drv_ctx, uint32_t n); +int +qat_sym_dp_enqueue_done_gen4(void *qp_data, uint8_t *drv_ctx, uint32_t n); + +int +qat_sym_dp_dequeue_done_gen4(void *qp_data, uint8_t *drv_ctx, uint32_t n); + int qat_sym_configure_raw_dp_ctx_gen1(void *_raw_dp_ctx, void *_ctx); -- 2.39.2 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-07-24 12:29:20.924881196 +0100 +++ 0001-crypto-qat-fix-GEN4-write.patch 2024-07-24 12:29:20.623023153 +0100 @@ -1 +1 @@ -From c355c2d8e65f02fa9621249c9b2a111477230c89 Mon Sep 17 00:00:00 2001 +From e793a7063f95d32916301282a820ffb16933b25e Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit c355c2d8e65f02fa9621249c9b2a111477230c89 ] + @@ -12 +13,0 @@ -Cc: stable@dpdk.org @@ -22 +23 @@ -index 5e808a60bf..6a5d6e78b9 100644 +index b219a418ba..52218e5a0a 100644 @@ -31,3 +32,3 @@ - - static struct rte_cryptodev_capabilities qat_sym_crypto_legacy_caps_gen4[] = { -@@ -233,6 +234,78 @@ qat_sym_build_op_aead_gen4(void *in_op, struct qat_sym_session *ctx, + static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen4[] = { + QAT_SYM_CIPHER_CAP(AES_CBC, +@@ -223,6 +224,78 @@ qat_sym_build_op_aead_gen4(void *in_op, struct qat_sym_session *ctx, @@ -109 +110 @@ - int + static int @@ -112 +113 @@ -@@ -390,11 +463,51 @@ qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void *_ctx) +@@ -383,11 +456,51 @@ qat_sym_configure_raw_dp_ctx_gen4(void *_raw_dp_ctx, void *_ctx) @@ -169 +170 @@ -index 1f5d2583c4..2c5816e696 100644 +index 2b1b0eb717..1acb0c4985 100644 @@ -172 +173 @@ -@@ -1040,6 +1040,12 @@ qat_sym_dp_enqueue_done_gen1(void *qp_data, uint8_t *drv_ctx, uint32_t n); +@@ -927,6 +927,12 @@ qat_sym_dp_enqueue_done_gen1(void *qp_data, uint8_t *drv_ctx, uint32_t n);