From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62E4345B14 for ; Fri, 11 Oct 2024 18:45:16 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 59536402F2; Fri, 11 Oct 2024 18:45:16 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by mails.dpdk.org (Postfix) with ESMTP id 2E62B402DE; Fri, 11 Oct 2024 18:45:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728665113; x=1760201113; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PlKIZ1/EHO6VSDd77XWQF2FKBkfHGv2sFfnzBEE+vJw=; b=T5zDXbMfZmB0JYz9dkry7bDIGXd7S8hCE2/G6PfdXLOX0r0/toYiykmJ vrr48kMoF55CnyOs7NAoL0GL65vzVJbnWT7uDBE9ESGR+NfxJTPr8GQKc JxdwY4/fzJ6eZckwaWAG29Jsk/H3waw4/yLzxCs8chjllhoY6AmJdjZIB KtPb4TmuU7h4+L2VFqxdtM/y5iqDvrgQyS29F9q3SyNvZvKk8JUwEJJZA luuB4FZ3NOXvTp+AlmC0gUnqpBLyGJEu9Do7kHflwzOSbubc03LkV/iSX TAcd9H73mqL73jj0OnplDjqLUYyN7CirT7Uw1pP7TpruvhQdFs3aDPMAF g==; X-CSE-ConnectionGUID: VOJ3mDuMTnykuUWLIN+Npw== X-CSE-MsgGUID: n7NOBeX3RKG8+aBI0YMAXw== X-IronPort-AV: E=McAfee;i="6700,10204,11222"; a="53477048" X-IronPort-AV: E=Sophos;i="6.11,196,1725346800"; d="scan'208";a="53477048" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Oct 2024 09:45:12 -0700 X-CSE-ConnectionGUID: pmAVHTzkTIuEj/A6Q1zuMg== X-CSE-MsgGUID: vQ3oS5KfTq2W4ebGjFjwsQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,196,1725346800"; d="scan'208";a="76609283" Received: from unknown (HELO silpixa00401385.ir.intel.com) ([10.237.214.25]) by fmviesa007.fm.intel.com with ESMTP; 11 Oct 2024 09:45:11 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: Jacob Keller , stable@dpdk.org, Bruce Richardson Subject: [PATCH 1/9] net/ice/base: re-enable bypass mode for E822 Date: Fri, 11 Oct 2024 17:44:51 +0100 Message-ID: <20241011164459.1987538-2-bruce.richardson@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241011164459.1987538-1-bruce.richardson@intel.com> References: <20241011164459.1987538-1-bruce.richardson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org From: Jacob Keller When removing bypass mode, the code for E822 bypass was completely removed in error. This code should be maintained in DPDK so re-add the necessary functions. Fixes: ce9ad8c5bc6d ("net/ice/base: remove PHY port timer bypass mode") Cc: stable@dpdk.org Signed-off-by: Jacob Keller Signed-off-by: Bruce Richardson --- drivers/net/ice/base/ice_ptp_hw.c | 117 ++++++++++++++++++++++++++++-- drivers/net/ice/base/ice_ptp_hw.h | 2 +- drivers/net/ice/ice_ethdev.c | 2 +- 3 files changed, 113 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 2a112fea12..1e92e5ff21 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -4468,18 +4468,103 @@ ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset) return 0; } +/** + * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode + * @hw: pointer to the HW struct + * @port: the PHY port to configure + * + * Calculate and program the fixed Tx offset, and indicate that the offset is + * ready. This can be used when operating in bypass mode. + */ +static int ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port) +{ + enum ice_ptp_link_spd link_spd; + enum ice_ptp_fec_mode fec_mode; + u64 total_offset; + int err; + + err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); + if (err) + return err; + + total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd); + + /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L + * register, then indicate that the Tx offset is ready. After this, + * timestamps will be enabled. + * + * Note that this skips including the more precise offsets generated + * by the Vernier calibration. + */ + + err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L, + total_offset); + if (err) + return err; + + err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1); + if (err) + return err; + + return ICE_SUCCESS; +} + +/** + * ice_phy_cfg_rx_offset_e822 - Configure fixed Rx offset for bypass mode + * @hw: pointer to the HW struct + * @port: the PHY port to configure + * + * Calculate and program the fixed Rx offset, and indicate that the offset is + * ready. This can be used when operating in bypass mode. + */ +static int ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port) +{ + enum ice_ptp_link_spd link_spd; + enum ice_ptp_fec_mode fec_mode; + u64 total_offset; + int err; + + err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); + if (err) + return err; + + total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd); + + /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L + * register, then indicate that the Rx offset is ready. After this, + * timestamps will be enabled. + * + * Note that this skips including the more precise offsets generated + * by Vernier calibration. + */ + err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L, + total_offset); + if (err) + return err; + + err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1); + if (err) + return err; + + return ICE_SUCCESS; +} + /** * ice_start_phy_timer_e822 - Start the PHY clock timer * @hw: pointer to the HW struct * @port: the PHY port to start + * @bypass: if true, start the PHY in bypass mode * * Start the clock of a PHY port. This must be done as part of the flow to * re-calibrate Tx and Rx timestamping offsets whenever the clock time is * initialized or when link speed changes. * - * Hardware will take Vernier measurements on Tx or Rx of packets. + * Bypass mode enables timestamps immediately without waiting for Vernier + * calibration to complete. Hardware will still continue taking Vernier + * measurements on Tx or Rx of packets, but they will not be applied to + * timestamps. */ -int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port) +int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) { u32 lo, hi, val; u64 incval; @@ -4544,15 +4629,35 @@ int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port) ice_ptp_exec_tmr_cmd(hw); + if (bypass) { + /* Enter BYPASS mode, enabling timestamps immediately. */ + val |= P_REG_PS_BYPASS_MODE_M; + err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); + if (err) + return err; + } + val |= P_REG_PS_ENA_CLK_M; err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); if (err) return err; - val |= P_REG_PS_LOAD_OFFSET_M; - err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); - if (err) - return err; + if (bypass) { + /* Program the fixed Tx offset */ + err = ice_phy_cfg_fixed_tx_offset_e822(hw, port); + if (err) + return err; + + /* Program the fixed Rx offset */ + err = ice_phy_cfg_fixed_rx_offset_e822(hw, port); + if (err) + return err; + } else { + val |= P_REG_PS_LOAD_OFFSET_M; + err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); + if (err) + return err; + } ice_ptp_exec_tmr_cmd(hw); diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 5d6636c0d1..534e05a8dd 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -277,7 +277,7 @@ ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port, void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port); int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset); -int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port); +int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass); int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port); int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port); int diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 61bff016be..2f9bcbd3a5 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -2540,7 +2540,7 @@ ice_dev_init(struct rte_eth_dev *dev) ice_ptp_init_phy_model(hw); if (hw->phy_model == ICE_PHY_E822) { - ret = ice_start_phy_timer_e822(hw, hw->pf_id); + ret = ice_start_phy_timer_e822(hw, hw->pf_id, true); if (ret) PMD_INIT_LOG(ERR, "Failed to start phy timer"); } -- 2.43.0