From: Gregory Etelson <getelson@nvidia.com>
To: <dev@dpdk.org>
Cc: getelson@nvidia.com, <mkashani@nvidia.com>,
rasland@nvidia.com, stable@dpdk.org,
"Suanming Mou" <suanmingm@nvidia.com>,
"Dariusz Sosnowski" <dsosnowski@nvidia.com>,
"Viacheslav Ovsiienko" <viacheslavo@nvidia.com>,
"Bing Zhao" <bingz@nvidia.com>, "Ori Kam" <orika@nvidia.com>,
"Matan Azrad" <matan@nvidia.com>
Subject: [PATCH] net/mlx5: fix GRE item translation for root table
Date: Sun, 27 Oct 2024 14:39:16 +0200 [thread overview]
Message-ID: <20241027123916.114037-1-getelson@nvidia.com> (raw)
Flow items translations for the root tables reuses DV code.
DV GRE item translation did not initiate item mask for HWS template.
Fixes: cd4ab742064a ("net/mlx5: split flow item matcher and value translation")
Cc: stable@dpdk.org
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Suanming Mou <suanmingm@nvidia.com>
---
drivers/net/mlx5/mlx5_flow_dv.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 201e215e4b..7c3a1d537a 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -9829,22 +9829,23 @@ flow_dv_translate_item_gre(void *key, const struct rte_flow_item *item,
} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
uint16_t protocol_m, protocol_v;
- if (key_type & MLX5_SET_MATCHER_M)
+ if (key_type & MLX5_SET_MATCHER_M) {
MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 0xff);
- else
+ if (!gre_m)
+ gre_m = &rte_flow_item_gre_mask;
+ gre_v = gre_m;
+ } else {
MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
IPPROTO_GRE);
- if (!gre_v) {
- gre_v = &empty_gre;
- gre_m = &empty_gre;
- } else {
- if (!gre_m)
+ if (!gre_v) {
+ gre_v = &empty_gre;
+ gre_m = &empty_gre;
+ } else if (!gre_m) {
gre_m = &rte_flow_item_gre_mask;
+ }
+ if (key_type == MLX5_SET_MATCHER_HS_V)
+ gre_m = gre_v;
}
- if (key_type & MLX5_SET_MATCHER_M)
- gre_v = gre_m;
- else if (key_type == MLX5_SET_MATCHER_HS_V)
- gre_m = gre_v;
gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
--
2.43.0
next reply other threads:[~2024-10-27 12:40 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-27 12:39 Gregory Etelson [this message]
2024-10-28 13:13 ` Raslan Darawsheh
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