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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2024 14:10:07.7883 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2ed70bd-cbb1-4baa-d252-08dcf691100a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7502 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org When DPDK copies flow items with the `rte_flow_conv` call, it assumes that size of PMD private data has pointer size - see patch [1] MLX5 PMD defined `struct mlx5_rte_flow_item_sq` as 32 bits. As the result, on 64 bits systems, when DPDK copied MLX5_RTE_FLOW_ITEM_TYPE_SQ item, the target buffer was assigned additional 32 bits. The patch expands size of `struct mlx5_rte_flow_item_sq` to 64 bits on 64 bits systems. [1]: commit 6cf72047332b ("ethdev: support flow elements with variable length") Fixes: 75a00812b18f ("net/mlx5: add hardware steering item translation") Cc: stable@dpdk.org Signed-off-by: Gregory Etelson Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5_flow.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index db56ae051d..9cf54c3a6a 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -168,6 +168,9 @@ struct mlx5_flow_action_copy_mreg { /* Matches on source queue. */ struct mlx5_rte_flow_item_sq { uint32_t queue; /* DevX SQ number */ +#ifdef RTE_ARCH_64 + uint32_t reserved; +#endif }; /* Map from registers to modify fields. */ -- 2.43.0