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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ1PEPF00001CE2.mail.protection.outlook.com (10.167.242.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8158.14 via Frontend Transport; Mon, 11 Nov 2024 06:39:44 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sun, 10 Nov 2024 22:39:35 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sun, 10 Nov 2024 22:39:32 -0800 From: Xueming Li To: Bing Zhao CC: , Viacheslav Ovsiienko , "dpdk stable" Subject: patch 'net/mlx5: workaround list management of Rx queue control' has been queued to stable release 23.11.3 Date: Mon, 11 Nov 2024 14:28:30 +0800 Message-ID: <20241111062847.216344-105-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241111062847.216344-1-xuemingl@nvidia.com> References: <20241111062847.216344-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE2:EE_|DM4PR12MB8474:EE_ X-MS-Office365-Filtering-Correlation-Id: c3069f50-95dd-457b-691d-08dd021ba0fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2024 06:39:44.4566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3069f50-95dd-457b-691d-08dd021ba0fe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8474 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.3 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/30/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=789faccc7ec15de2004468416d46ea1184c68f25 Thanks. Xueming Li --- >From 789faccc7ec15de2004468416d46ea1184c68f25 Mon Sep 17 00:00:00 2001 From: Bing Zhao Date: Tue, 23 Jul 2024 14:14:11 +0300 Subject: [PATCH] net/mlx5: workaround list management of Rx queue control Cc: Xueming Li [ upstream commit f957ac99643535fd218753f4f956fc9c5aadd23c ] The LIST_REMOVE macro only removes the entry from the list and updates list itself. The pointers of this entry are not reset to NULL to prevent the accessing for the 2nd time. In the previous fix for the memory accessing, the "rxq_ctrl" was removed from the list in a device private data when the "refcnt" was decreased to 0. Under only shared or non-shared queues scenarios, this was safe since all the "rxq_ctrl" entries were freed or kept. There is one case that shared and non-shared Rx queues are configured simultaneously, for example, a hairpin Rx queue cannot be shared. When closing the port that allocated the shared Rx queues' "rxq_ctrl", if the next entry is hairpin "rxq_ctrl", the hairpin "rxq_ctrl" will be freed directly with other resources. When trying to close the another port sharing the "rxq_ctrl", the LIST_REMOVE will be called again and cause some UFA issue. If the memory is no longer mapped, there will be a SIGSEGV. Adding a flag in the Rx queue private structure to remove the "rxq_ctrl" from the list only on the port/queue that allocated it. Fixes: bcc220cb57d7 ("net/mlx5: fix shared Rx queue list management") Signed-off-by: Bing Zhao Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_rx.h | 1 + drivers/net/mlx5/mlx5_rxq.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index d0ceae72ea..08ab0a042d 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -173,6 +173,7 @@ struct mlx5_rxq_ctrl { /* RX queue private data. */ struct mlx5_rxq_priv { uint16_t idx; /* Queue index. */ + bool possessor; /* Shared rxq_ctrl allocated for the 1st time. */ uint32_t refcnt; /* Reference counter. */ struct mlx5_rxq_ctrl *ctrl; /* Shared Rx Queue. */ LIST_ENTRY(mlx5_rxq_priv) owner_entry; /* Entry in shared rxq_ctrl. */ diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 1bb036afeb..e45cca9133 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -938,6 +938,7 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, rte_errno = ENOMEM; return -rte_errno; } + rxq->possessor = true; } rxq->priv = priv; rxq->idx = idx; @@ -2016,6 +2017,7 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 }; tmpl->rxq.idx = idx; rxq->hairpin_conf = *hairpin_conf; + rxq->possessor = true; mlx5_rxq_ref(dev, idx); LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next); return tmpl; @@ -2283,7 +2285,8 @@ mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx) RTE_ETH_QUEUE_STATE_STOPPED; } } else { /* Refcnt zero, closing device. */ - LIST_REMOVE(rxq_ctrl, next); + if (rxq->possessor) + LIST_REMOVE(rxq_ctrl, next); LIST_REMOVE(rxq, owner_entry); if (LIST_EMPTY(&rxq_ctrl->owners)) { if (!rxq_ctrl->is_hairpin) -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-11-11 14:23:09.970133241 +0800 +++ 0104-net-mlx5-workaround-list-management-of-Rx-queue-cont.patch 2024-11-11 14:23:05.292192836 +0800 @@ -1 +1 @@ -From f957ac99643535fd218753f4f956fc9c5aadd23c Mon Sep 17 00:00:00 2001 +From 789faccc7ec15de2004468416d46ea1184c68f25 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit f957ac99643535fd218753f4f956fc9c5aadd23c ] @@ -28 +30,0 @@ -Cc: stable@dpdk.org @@ -38 +40 @@ -index 7d144921ab..9bcb43b007 100644 +index d0ceae72ea..08ab0a042d 100644 @@ -46 +48 @@ - RTE_ATOMIC(uint32_t) refcnt; /* Reference counter. */ + uint32_t refcnt; /* Reference counter. */ @@ -50 +52 @@ -index f13fc3b353..c6655b7db4 100644 +index 1bb036afeb..e45cca9133 100644 @@ -61 +63 @@ -@@ -2015,6 +2016,7 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, +@@ -2016,6 +2017,7 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, @@ -69 +71 @@ -@@ -2282,7 +2284,8 @@ mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx) +@@ -2283,7 +2285,8 @@ mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)