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[204.195.96.226]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea61869bb2sm2916724a91.12.2024.11.18.10.22.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2024 10:22:11 -0800 (PST) From: Stephen Hemminger To: dev@dpdk.org Cc: Stephen Hemminger , ashish.jain@nxp.com, stable@dpdk.org, Hemant Agrawal Subject: [PATCH v2 12/19] crypto/dpaa2_sec: fix bitmask truncation Date: Mon, 18 Nov 2024 10:20:53 -0800 Message-ID: <20241118182153.87042-13-stephen@networkplumber.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241118182153.87042-1-stephen@networkplumber.org> References: <20241115060738.313190-1-stephen@networkplumber.org> <20241118182153.87042-1-stephen@networkplumber.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org The dqrr_held mask is 64 bit but updates were getting truncated because 1 is of type int (32 bit) and the result shift of int is of type int (32 bit); therefore any value >= 32 would get truncated. Link: https://pvs-studio.com/en/blog/posts/cpp/1183/ Fixes: a77db24643b7 ("crypto/dpaa2_sec: support atomic queues") Cc: ashish.jain@nxp.com Cc: stable@dpdk.org Signed-off-by: Stephen Hemminger Acked-by: Hemant Agrawal --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index ec6577f64c..7ad8fd47dd 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -1491,8 +1491,8 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops, if (*dpaa2_seqn((*ops)->sym->m_src)) { if (*dpaa2_seqn((*ops)->sym->m_src) & QBMAN_ENQUEUE_FLAG_DCA) { DPAA2_PER_LCORE_DQRR_SIZE--; - DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << - *dpaa2_seqn((*ops)->sym->m_src) & + DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << + *dpaa2_seqn((*ops)->sym->m_src) & QBMAN_EQCR_DCA_IDXMASK); } flags[loop] = *dpaa2_seqn((*ops)->sym->m_src); @@ -1772,7 +1772,7 @@ dpaa2_sec_set_enqueue_descriptor(struct dpaa2_queue *dpaa2_q, dq_idx = *dpaa2_seqn(m) - 1; qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0); DPAA2_PER_LCORE_DQRR_SIZE--; - DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx); + DPAA2_PER_LCORE_DQRR_HELD &= ~(UINT64_C(1) << dq_idx); } *dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN; } @@ -4055,7 +4055,7 @@ dpaa2_sec_process_atomic_event(struct qbman_swp *swp __rte_unused, dqrr_index = qbman_get_dqrr_idx(dq); *dpaa2_seqn(crypto_op->sym->m_src) = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index; DPAA2_PER_LCORE_DQRR_SIZE++; - DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index; + DPAA2_PER_LCORE_DQRR_HELD |= UINT64_C(1) << dqrr_index; DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = crypto_op->sym->m_src; ev->event_ptr = crypto_op; } -- 2.45.2